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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-10-15 12:23:29 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-10-15 12:23:29 +0000 |
| commit | 30b3211be7f4cdf44d5a630c580d019b8129a1ba (patch) | |
| tree | 8f998f5d96804eb07b5989f0db30bc6c708966d5 /os/hal/ports/STM32/STM32F0xx | |
| parent | 332f42a40565e965dab3eea8f15d917caae38f2e (diff) | |
| download | ChibiOS-30b3211be7f4cdf44d5a630c580d019b8129a1ba.tar.gz ChibiOS-30b3211be7f4cdf44d5a630c580d019b8129a1ba.tar.bz2 ChibiOS-30b3211be7f4cdf44d5a630c580d019b8129a1ba.zip | |
USART 3..6 support for STM32F030xC.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8361 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32F0xx')
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/hal_lld.h | 20 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/stm32_isr.h | 2 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/stm32_rcc.h | 106 |
3 files changed, 128 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.h b/os/hal/ports/STM32/STM32F0xx/hal_lld.h index a2f8662de..6255ddcc8 100644 --- a/os/hal/ports/STM32/STM32F0xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.h @@ -806,6 +806,26 @@ #define STM32_USART2CLK STM32_PCLK
/**
+ * @brief USART3 frequency.
+ */
+#define STM32_USART3CLK STM32_PCLK
+
+/**
+ * @brief USART4 frequency.
+ */
+#define STM32_UART4CLK STM32_PCLK
+
+/**
+ * @brief USART5 frequency.
+ */
+#define STM32_UART5CLK STM32_PCLK
+
+/**
+ * @brief USART6 frequency.
+ */
+#define STM32_USART6CLK STM32_PCLK
+
+/**
* @brief Timers clock.
*/
#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_isr.h b/os/hal/ports/STM32/STM32F0xx/stm32_isr.h index f3db0c5f5..f86cb20aa 100644 --- a/os/hal/ports/STM32/STM32F0xx/stm32_isr.h +++ b/os/hal/ports/STM32/STM32F0xx/stm32_isr.h @@ -66,9 +66,11 @@ */
#define STM32_USART1_HANDLER VectorAC
#define STM32_USART2_HANDLER VectorB0
+#define STM32_USART3456_HANDLER VectorB4
#define STM32_USART1_NUMBER 27
#define STM32_USART2_NUMBER 28
+#define STM32_USART3456_NUMBER 29
/*
* USB units.
diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h index f51687787..6ecb97f1b 100644 --- a/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h @@ -586,6 +586,112 @@ * @api
*/
#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
+
+/**
+ * @brief Enables the USART3 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
+
+/**
+ * @brief Disables the USART3 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp)
+
+/**
+ * @brief Resets the USART3 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
+
+/**
+ * @brief Enables the USART4 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_USART4EN, lp)
+
+/**
+ * @brief Disables the USART4 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_USART4EN, lp)
+
+/**
+ * @brief Resets the USART4 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_USART4RST)
+
+/**
+ * @brief Enables the USART5 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_USARTS5EN, lp)
+
+/**
+ * @brief Disables the USART5 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_USART5EN, lp)
+
+/**
+ * @brief Resets the USART5 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_USART5RST)
+
+/**
+ * @brief Enables the USART6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp)
+
+/**
+ * @brief Disables the USART6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART6(lp) rccDisableAPB2(RCC_APB2ENR_USART6EN, lp)
+
+/**
+ * @brief Resets the USART6 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST)
/** @} */
/**
|