More ADCv4 code.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11265 35acf78f-673a-0410-8e92-d51de3d6d3f4

2 files changed, 307 insertions, 628 deletions

diff --git a/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c b/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c
index 94811895e..5e98cfbd8 100644
--- a/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c
+++ b/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.c
@@ -30,77 +30,53 @@
 /* Driver local definitions.                                                 */

 /*===========================================================================*/

 

-#define ADC1_DMA_CHANNEL                                                    \

-  STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN)

-

-#define ADC2_DMA_CHANNEL                                                    \

-  STM32_DMA_GETCHANNEL(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_CHN)

-

-#define ADC3_DMA_CHANNEL                                                    \

-  STM32_DMA_GETCHANNEL(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_CHN)

-

-#define ADC4_DMA_CHANNEL                                                    \

-  STM32_DMA_GETCHANNEL(STM32_ADC_ADC4_DMA_STREAM, STM32_ADC4_DMA_CHN)

-

-#if STM32_ADC_DUAL_MODE

-#if STM32_ADC_COMPACT_SAMPLES

+#if STM32_ADC_DUAL_MODE == TRUE

+#if STM32_ADC_COMPACT_SAMPLES == TRUE

 /* Compact type dual mode.*/

 #define ADC_DMA_SIZE    (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)

-#define ADC_DMA_MDMA    ADC_CCR_MDMA_HWORD

+#define ADC_DMA_DAMDF   ADC_CCR_DAMDF_HWORD

 

-#else /* !STM32_ADC_COMPACT_SAMPLES */

+#else /* STM32_ADC_COMPACT_SAMPLES == FALSE */

 /* Large type dual mode.*/

 #define ADC_DMA_SIZE    (STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_PSIZE_WORD)

-#define ADC_DMA_MDMA    ADC_CCR_MDMA_WORD

+#define ADC_DMA_DAMDF   ADC_CCR_DAMDF_WORD

 #endif /* !STM32_ADC_COMPACT_SAMPLES */

 

-#else /* !STM32_ADC_DUAL_MODE */

+#else /* STM32_ADC_DUAL_MODE == FALSE */

 #if STM32_ADC_COMPACT_SAMPLES

 /* Compact type single mode.*/

 #define ADC_DMA_SIZE    (STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE)

-#define ADC_DMA_MDMA    ADC_CCR_MDMA_DISABLED

+#define ADC_DMA_DAMDF   ADC_CCR_DAMDF_DISABLED

 

-#else /* !STM32_ADC_COMPACT_SAMPLES */

+#else /* STM32_ADC_COMPACT_SAMPLES == FALSE */

 /* Large type single mode.*/

 #define ADC_DMA_SIZE    (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)

-#define ADC_DMA_MDMA    ADC_CCR_MDMA_DISABLED

-#endif /* !STM32_ADC_COMPACT_SAMPLES */

-#endif /* !STM32_ADC_DUAL_MODE */

+#define ADC_DMA_DAMDF   ADC_CCR_DAMDF_DISABLED

+#endif /* STM32_ADC_COMPACT_SAMPLES == FALSE */

+#endif /* STM32_ADC_DUAL_MODE == FALSE */

 

 /*===========================================================================*/

 /* Driver exported variables.                                                */

 /*===========================================================================*/

 

 /** @brief ADC1 driver identifier.*/

-#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)

+#if STM32_ADC_USE_ADC12 || defined(__DOXYGEN__)

 ADCDriver ADCD1;

 #endif

 

-/** @brief ADC2 driver identifier.*/

-#if STM32_ADC_USE_ADC2 || defined(__DOXYGEN__)

-ADCDriver ADCD2;

-#endif

-

 /** @brief ADC3 driver identifier.*/

 #if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)

 ADCDriver ADCD3;

 #endif

 

-/** @brief ADC4 driver identifier.*/

-#if STM32_ADC_USE_ADC4 || defined(__DOXYGEN__)

-ADCDriver ADCD4;

-#endif

-

 /*===========================================================================*/

 /* Driver local variables and types.                                         */

 /*===========================================================================*/

 

 static const ADCConfig default_config = {

-  difsel: 0

+  .difsel = 0U

 };

 

-static uint32_t clkmask;

-

 /*===========================================================================*/

 /* Driver local functions.                                                   */

 /*===========================================================================*/

@@ -112,23 +88,11 @@ static uint32_t clkmask;
  */

 static void adc_lld_vreg_on(ADCDriver *adcp) {

 

-#if defined(STM32F3XX)

-  adcp->adcm->CR = 0;   /* RM 12.4.3.*/

-  adcp->adcm->CR = ADC_CR_ADVREGEN_0;

-#if STM32_ADC_DUAL_MODE

-  adcp->adcs->CR = ADC_CR_ADVREGEN_0;

-#endif

-  osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 10));

-#endif

-

-#if defined(STM32L4XX)

-  adcp->adcm->CR = 0;   /* RM 16.3.6.*/

   adcp->adcm->CR = ADC_CR_ADVREGEN;

 #if STM32_ADC_DUAL_MODE

   adcp->adcs->CR = ADC_CR_ADVREGEN;

 #endif

-  osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 20));

-#endif

+  osalSysPolledDelayX(OSAL_US2RTC(STM32_SYS_CK, 10U));

 }

 

 /**

@@ -138,23 +102,10 @@ static void adc_lld_vreg_on(ADCDriver *adcp) {
  */

 static void adc_lld_vreg_off(ADCDriver *adcp) {

 

-#if defined(STM32F3XX)

-  adcp->adcm->CR = 0;   /* RM 12.4.3.*/

-  adcp->adcm->CR = ADC_CR_ADVREGEN_1;

-#if STM32_ADC_DUAL_MODE

-  adcp->adcs->CR = 0;

-  adcp->adcs->CR = ADC_CR_ADVREGEN_1;

-#endif

-#endif

-

-#if defined(STM32L4XX)

-  adcp->adcm->CR = 0;   /* RM 12.4.3.*/

   adcp->adcm->CR = ADC_CR_DEEPPWD;

 #if STM32_ADC_DUAL_MODE

-  adcp->adcs->CR = 0;

   adcp->adcs->CR = ADC_CR_DEEPPWD;

 #endif

-#endif

 }

 

 /**

@@ -164,27 +115,16 @@ static void adc_lld_vreg_off(ADCDriver *adcp) {
  */

 static void adc_lld_analog_on(ADCDriver *adcp) {

 

-#if defined(STM32F3XX)

-  adcp->adcm->CR |= ADC_CR_ADEN;

-  while ((adcp->adcm->ISR & ADC_ISR_ADRD) == 0)

-    ;

-#if STM32_ADC_DUAL_MODE

-  adcp->adcs->CR |= ADC_CR_ADEN;

-  while ((adcp->adcs->ISR & ADC_ISR_ADRD) == 0)

-    ;

-#endif

-#endif

-

-#if defined(STM32L4XX)

+  adcp->adcm->ISR = ADC_ISR_ADRD;

   adcp->adcm->CR |= ADC_CR_ADEN;

-  while ((adcp->adcm->ISR & ADC_ISR_ADRDY) == 0)

+  while ((adcp->adcm->ISR & ADC_ISR_ADRD) == 0U)

     ;

 #if STM32_ADC_DUAL_MODE

+  adcp->adcs->ISR = ADC_ISR_ADRD;

   adcp->adcs->CR |= ADC_CR_ADEN;

-  while ((adcp->adcs->ISR & ADC_ISR_ADRDY) == 0)

+  while ((adcp->adcs->ISR & ADC_ISR_ADRD) == 0U)

     ;

 #endif

-#endif

 }

 

 /**

@@ -195,11 +135,11 @@ static void adc_lld_analog_on(ADCDriver *adcp) {
 static void adc_lld_analog_off(ADCDriver *adcp) {

 

   adcp->adcm->CR |= ADC_CR_ADDIS;

-  while ((adcp->adcm->CR & ADC_CR_ADDIS) != 0)

+  while ((adcp->adcm->CR & ADC_CR_ADDIS) != 0U)

     ;

 #if STM32_ADC_DUAL_MODE

   adcp->adcs->CR |= ADC_CR_ADDIS;

-  while ((adcp->adcs->CR & ADC_CR_ADDIS) != 0)

+  while ((adcp->adcs->CR & ADC_CR_ADDIS) != 0U)

     ;

 #endif

 }

@@ -211,31 +151,16 @@ static void adc_lld_analog_off(ADCDriver *adcp) {
  */

 static void adc_lld_calibrate(ADCDriver *adcp) {

 

-#if defined(STM32F3XX)

-  osalDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN_0, "invalid register state");

+ osalDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN, "invalid register state");

   adcp->adcm->CR |= ADC_CR_ADCAL;

-  while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0)

-    ;

-#if STM32_ADC_DUAL_MODE

-  osalDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN_0, "invalid register state");

-  adcp->adcs->CR |= ADC_CR_ADCAL;

-  while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0)

-    ;

-#endif

-#endif

-

-#if defined(STM32L4XX)

-  osalDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN, "invalid register state");

-  adcp->adcm->CR |= ADC_CR_ADCAL;

-  while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0)

+  while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0U)

     ;

 #if STM32_ADC_DUAL_MODE

   osalDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN, "invalid register state");

   adcp->adcs->CR |= ADC_CR_ADCAL;

-  while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0)

+  while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0U)

     ;

 #endif

-#endif

 }

 

 /**

@@ -296,7 +221,7 @@ static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
     /* Note, an overflow may occur after the conversion ended before the driver

        is able to stop the ADC, this is why the DMA channel is checked too.*/

     if ((isr & ADC_ISR_OVR) &&

-        (dmaStreamGetTransactionSize(adcp->dmastp) > 0)) {

+        (dmaStreamGetTransactionSize(adcp->data.dma) > 0)) {

       /* ADC overflow condition, this could happen only if the DMA is unable

          to read data fast enough.*/

       _adc_isr_error_code(adcp, ADC_ERR_OVERFLOW);

@@ -320,18 +245,18 @@ static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
 /* Driver interrupt handlers.                                                */

 /*===========================================================================*/

 

-#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 || defined(__DOXYGEN__)

+#if (STM32_ADC_USE_ADC12 == TRUE) || defined(__DOXYGEN__)

 /**

  * @brief   ADC1/ADC2 interrupt handler.

  *

  * @isr

  */

-OSAL_IRQ_HANDLER(STM32_ADC1_HANDLER) {

+OSAL_IRQ_HANDLER(STM32_ADC12_HANDLER) {

   uint32_t isr;

 

   OSAL_IRQ_PROLOGUE();

 

-#if STM32_ADC_DUAL_MODE

+#if STM32_ADC_DUAL_MODE == TRUE

 

   isr  = ADC1->ISR;

   isr |= ADC2->ISR;

@@ -342,33 +267,24 @@ OSAL_IRQ_HANDLER(STM32_ADC1_HANDLER) {
 #endif

   adc_lld_serve_interrupt(&ADCD1, isr);

 

-#else /* !STM32_ADC_DUAL_MODE */

+#else /* STM32_ADC_DUAL_MODE = FALSE */

 

-#if STM32_ADC_USE_ADC1

+#if STM32_ADC_USE_ADC12 == TRUE

   isr  = ADC1->ISR;

   ADC1->ISR = isr;

-#if defined(STM32_ADC_ADC1_IRQ_HOOK)

-  STM32_ADC_ADC1_IRQ_HOOK

+#if defined(STM32_ADC_ADC12_IRQ_HOOK)

+  STM32_ADC_ADC12_IRQ_HOOK

 #endif

   adc_lld_serve_interrupt(&ADCD1, isr);

 #endif

 

-#if STM32_ADC_USE_ADC2

-  isr  = ADC2->ISR;

-  ADC2->ISR = isr;

-#if defined(STM32_ADC_ADC2_IRQ_HOOK)

-  STM32_ADC_ADC2_IRQ_HOOK

-#endif

-  adc_lld_serve_interrupt(&ADCD2, isr);

-#endif

-

-#endif /* !STM32_ADC_DUAL_MODE */

+#endif /* STM32_ADC_DUAL_MODE == FALSE */

 

   OSAL_IRQ_EPILOGUE();

 }

-#endif /* STM32_ADC_USE_ADC1 */

+#endif /* STM32_ADC_USE_ADC12 == TRUE */

 

-#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)

+#if (STM32_ADC_USE_ADC3 == TRUE) || defined(__DOXYGEN__)

 /**

  * @brief   ADC3 interrupt handler.

  *

@@ -388,47 +304,7 @@ OSAL_IRQ_HANDLER(STM32_ADC3_HANDLER) {
 

   OSAL_IRQ_EPILOGUE();

 }

-

-#if STM32_ADC_DUAL_MODE

-/**

- * @brief   ADC4 interrupt handler (as ADC3 slave).

- *

- * @isr

- */

-OSAL_IRQ_HANDLER(STM32_ADC4_HANDLER) {

-  uint32_t isr;

-

-  OSAL_IRQ_PROLOGUE();

-

-  isr  = ADC4->ISR;

-  ADC4->ISR = isr;

-

-  adc_lld_serve_interrupt(&ADCD3, isr);

-

-  OSAL_IRQ_EPILOGUE();

-}

-#endif /* STM32_ADC_DUAL_MODE */

-#endif /* STM32_ADC_USE_ADC3 */

-

-#if STM32_ADC_USE_ADC4 || defined(__DOXYGEN__)

-/**

- * @brief   ADC4 interrupt handler.

- *

- * @isr

- */

-OSAL_IRQ_HANDLER(STM32_ADC4_HANDLER) {

-  uint32_t isr;

-

-  OSAL_IRQ_PROLOGUE();

-

-  isr  = ADC4->ISR;

-  ADC4->ISR = isr;

-

-  adc_lld_serve_interrupt(&ADCD4, isr);

-

-  OSAL_IRQ_EPILOGUE();

-}

-#endif /* STM32_ADC_USE_ADC4 */

+#endif /* STM32_ADC_USE_ADC3 == TRUE */

 

 /*===========================================================================*/

 /* Driver exported functions.                                                */

@@ -441,48 +317,24 @@ OSAL_IRQ_HANDLER(STM32_ADC4_HANDLER) {
  */

 void adc_lld_init(void) {

 

-  clkmask = 0;

-

-#if STM32_ADC_USE_ADC1

+#if STM32_ADC_USE_ADC12 == TRUE

   /* Driver initialization.*/

   adcObjectInit(&ADCD1);

-#if defined(ADC1_2_COMMON)

-  ADCD1.adcc = ADC1_2_COMMON;

-#elif defined(ADC123_COMMON)

-  ADCD1.adcc = ADC123_COMMON;

-#else

-  ADCD1.adcc = ADC1_COMMON;

-#endif

-  ADCD1.adcm    = ADC1;

+  ADCD1.adcc     = ADC12_COMMON;

+  ADCD1.adcm     = ADC1;

 #if STM32_ADC_DUAL_MODE

-  ADCD1.adcs    = ADC2;

-#endif

-  ADCD1.dmastp  = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);

-  ADCD1.dmamode = ADC_DMA_SIZE |

-                  STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |

-                  STM32_DMA_CR_DIR_P2M |

-                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |

-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;

-#endif /* STM32_ADC_USE_ADC1 */

-

-#if STM32_ADC_USE_ADC2

-  /* Driver initialization.*/

-  adcObjectInit(&ADCD2);

-#if defined(ADC1_2_COMMON)

-  ADCD2.adcc = ADC1_2_COMMON;

-#elif defined(ADC123_COMMON)

-  ADCD2.adcc = ADC123_COMMON;

-#endif

-  ADCD2.adcm    = ADC2;

-  ADCD2.dmastp  = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM);

-  ADCD2.dmamode = ADC_DMA_SIZE |

-                  STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) |

-                  STM32_DMA_CR_DIR_P2M |

-                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |

-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;

-#endif /* STM32_ADC_USE_ADC2 */

-

-#if STM32_ADC_USE_ADC3

+  ADCD1.adcs     = ADC2;

+#endif

+  ADCD1.data.dma = STM32_DMA_STREAM(STM32_ADC_ADC12_DMA_CHANNEL);

+  ADCD1.dmamode  = ADC_DMA_SIZE |

+                   STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) |

+                   STM32_DMA_CR_DIR_P2M |

+                   STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |

+                   STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;

+  nvicEnableVector(STM32_ADC12_NUMBER, STM32_ADC_ADC12_IRQ_PRIORITY);

+#endif /* STM32_ADC_USE_ADC12 == TRUE */

+

+#if STM32_ADC_USE_ADC3 == TRUE

   /* Driver initialization.*/

   adcObjectInit(&ADCD3);

 #if defined(ADC3_4_COMMON)

@@ -502,74 +354,24 @@ void adc_lld_init(void) {
                   STM32_DMA_CR_DIR_P2M |

                   STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |

                   STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;

-#endif /* STM32_ADC_USE_ADC3 */

-

-#if STM32_ADC_USE_ADC4

-  /* Driver initialization.*/

-  adcObjectInit(&ADCD4);

-  ADCD4.adcc = ADC3_4_COMMON;

-  ADCD4.adcm    = ADC4;

-  ADCD4.dmastp  = STM32_DMA_STREAM(STM32_ADC_ADC4_DMA_STREAM);

-  ADCD4.dmamode = ADC_DMA_SIZE |

-                  STM32_DMA_CR_PL(STM32_ADC_ADC4_DMA_PRIORITY) |

-                  STM32_DMA_CR_DIR_P2M |

-                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |

-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;

-#endif /* STM32_ADC_USE_ADC4 */

-

-  /* IRQs setup.*/

-#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2

-  nvicEnableVector(STM32_ADC1_NUMBER, STM32_ADC_ADC12_IRQ_PRIORITY);

-#endif

-#if STM32_ADC_USE_ADC3

   nvicEnableVector(STM32_ADC3_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY);

-#if STM32_ADC_DUAL_MODE

-  nvicEnableVector(STM32_ADC4_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY);

-#endif

-#endif

-#if STM32_ADC_USE_ADC4

-  nvicEnableVector(STM32_ADC4_NUMBER, STM32_ADC_ADC3_IRQ_PRIORITY);

-#endif

+#endif /* STM32_ADC_USE_ADC3 == TRUE */

 

   /* ADC units pre-initializations.*/

-#if defined(STM32F3XX)

-#if STM32_HAS_ADC1 && STM32_HAS_ADC2

-#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2

+#if (STM32_HAS_ADC1 == TRUE) && (STM32_HAS_ADC2 == TRUE)

+#if STM32_ADC_USE_ADC12 == TRUE

   rccEnableADC12(false);

   rccResetADC12();

-  ADC1_2_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;

+  ADC12_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_DAMDF;

   rccDisableADC12();

 #endif

-#else

-#if STM32_ADC_USE_ADC1

-  rccEnableADC12(false);

-  rccResetADC12();

-  ADC1_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;

-  rccDisableADC12();

-#endif

-#endif

-#if STM32_ADC_USE_ADC3 || STM32_ADC_USE_ADC4

-  rccEnableADC34(false);

-  rccResetADC34();

-  ADC3_4_COMMON->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;

-  rccDisableADC34();

+#if STM32_ADC_USE_ADC3 == TRUE

+  rccEnableADC3(false);

+  rccResetADC3();

+  ADC3_COMMON->CCR = STM32_ADC_ADC3_CLOCK_MODE | ADC_DMA_DAMDF;

+  rccDisableADC3();

 #endif

 #endif

-

-#if defined(STM32L4XX)

-  rccEnableADC123(false);

-  rccResetADC123();

-

-#if defined(ADC1_2_COMMON)

-  ADC1_2_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;

-#elif defined(ADC123_COMMON)

-  ADC123_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;

-#else

-  ADC1_COMMON->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;

-#endif

-

-  rccDisableADC123();

-#endif

 }

 

 /**

@@ -588,91 +390,39 @@ void adc_lld_start(ADCDriver *adcp) {
 

   /* If in stopped state then enables the ADC and DMA clocks.*/

   if (adcp->state == ADC_STOP) {

-#if STM32_ADC_USE_ADC1

+#if STM32_ADC_USE_ADC12 == TRUE

     if (&ADCD1 == adcp) {

       bool b;

-      b = dmaStreamAllocate(adcp->dmastp,

-                            STM32_ADC_ADC1_DMA_IRQ_PRIORITY,

-                            (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,

-                            (void *)adcp);

-      osalDbgAssert(!b, "stream already allocated");

-

-      clkmask |= (1 << 0);

-#if defined(STM32F3XX)

-      rccEnableADC12(false);

-#endif

-#if defined(STM32L4XX)

-      rccEnableADC123(false);

-#endif

-    }

-#endif /* STM32_ADC_USE_ADC1 */

-

-#if STM32_ADC_USE_ADC2

-    if (&ADCD2 == adcp) {

-      bool b;

-      b = dmaStreamAllocate(adcp->dmastp,

-                            STM32_ADC_ADC2_DMA_IRQ_PRIORITY,

+      b = dmaStreamAllocate(adcp->data.dma,

+                            STM32_ADC_ADC12_IRQ_PRIORITY,

                             (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,

                             (void *)adcp);

       osalDbgAssert(!b, "stream already allocated");

-

-      clkmask |= (1 << 1);

-#if defined(STM32F3XX)

       rccEnableADC12(false);

-#endif

-#if defined(STM32L4XX)

-      rccEnableADC123(false);

-#endif

     }

-#endif /* STM32_ADC_USE_ADC2 */

+#endif /* STM32_ADC_USE_ADC12 == TRUE */

 

-#if STM32_ADC_USE_ADC3

+#if STM32_ADC_USE_ADC3 == TRUE

     if (&ADCD3 == adcp) {

       bool b;

       b = dmaStreamAllocate(adcp->dmastp,

-                            STM32_ADC_ADC3_DMA_IRQ_PRIORITY,

+                            STM32_ADC_ADC3_IRQ_PRIORITY,

                             (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,

                             (void *)adcp);

       osalDbgAssert(!b, "stream already allocated");

-

-      clkmask |= (1 << 2);

-#if defined(STM32F3XX)

-      rccEnableADC34(false);

-#endif

-#if defined(STM32L4XX)

-      rccEnableADC123(false);

-#endif

+      rccEnableADC3(false);

     }

-#endif /* STM32_ADC_USE_ADC3 */

-

-#if STM32_ADC_USE_ADC4

-    if (&ADCD4 == adcp) {

-      bool b;

-      b = dmaStreamAllocate(adcp->dmastp,

-                            STM32_ADC_ADC4_DMA_IRQ_PRIORITY,

-                            (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,

-                            (void *)adcp);

-      osalDbgAssert(!b, "stream already allocated");

-

-      clkmask |= (1 << 3);

-#if defined(STM32F3XX)

-      rccEnableADC34(false);

-#endif

-#if defined(STM32L4XX)

-      rccEnableADC123(false);

-#endif

-    }

-#endif /* STM32_ADC_USE_ADC4 */

+#endif /* STM32_ADC_USE_ADC3 == TRUE */

 

     /* Setting DMA peripheral-side pointer.*/

-#if STM32_ADC_DUAL_MODE

-    dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcc->CDR);

+#if STM32_ADC_DUAL_MODE == TRUE

+    dmaStreamSetPeripheral(adcp->data.dma, &adcp->adcc->CDR);

 #else

-    dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcm->DR);

+    dmaStreamSetPeripheral(adcp->data.dma, &adcp->adcm->DR);

 #endif

 

     /* Differential channels setting.*/

-#if STM32_ADC_DUAL_MODE

+#if STM32_ADC_DUAL_MODE == TRUE

     adcp->adcm->DIFSEL = adcp->config->difsel;

     adcp->adcs->DIFSEL = adcp->config->difsel;

 #else

@@ -701,7 +451,7 @@ void adc_lld_stop(ADCDriver *adcp) {
   if (adcp->state == ADC_READY) {

 

     /* Releasing the associated DMA channel.*/

-    dmaStreamRelease(adcp->dmastp);

+    dmaStreamRelease(adcp->data.dma);

 

     /* Stopping the ongoing conversion, if any.*/

     adc_lld_stop_adc(adcp);

@@ -710,68 +460,19 @@ void adc_lld_stop(ADCDriver *adcp) {
     adc_lld_analog_off(adcp);

     adc_lld_vreg_off(adcp);

 

-#if defined(STM32L4XX)

-    /* Resetting CCR options except default ones.*/

-    adcp->adcc->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;

-#endif

-

-#if STM32_ADC_USE_ADC1

+#if STM32_ADC_USE_ADC12 == TRUE

     if (&ADCD1 == adcp) {

-#if defined(STM32F3XX)

       /* Resetting CCR options except default ones.*/

-      adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;

-#endif

-      clkmask &= ~(1 << 0);

-    }

-#endif

-

-#if STM32_ADC_USE_ADC2

-    if (&ADCD2 == adcp) {

-#if defined(STM32F3XX)

-      /* Resetting CCR options except default ones.*/

-      adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;

-#endif

-      clkmask &= ~(1 << 1);

+      adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_DAMDF;

+      rccDisableADC12();

     }

 #endif

 

-#if STM32_ADC_USE_ADC3

+#if STM32_ADC_USE_ADC3 == TRUE

     if (&ADCD3 == adcp) {

-#if defined(STM32F3XX)

-      /* Resetting CCR options except default ones.*/

-      adcp->adcc->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;

-#endif

-      clkmask &= ~(1 << 2);

-    }

-#endif

-

-#if STM32_ADC_USE_ADC4

-    if (&ADCD4 == adcp) {

-#if defined(STM32F3XX)

       /* Resetting CCR options except default ones.*/

-      adcp->adcc->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;

-#endif

-      clkmask &= ~(1 << 3);

-    }

-#endif

-

-#if defined(STM32F3XX)

-#if STM32_HAS_ADC1 || STM32_HAS_ADC2

-    if ((clkmask & 0x3) == 0) {

-      rccDisableADC12();

-    }

-#endif

-

-#if STM32_HAS_ADC3 || STM32_HAS_ADC4

-    if ((clkmask & 0xC) == 0) {

-      rccDisableADC34();

-    }

-#endif

-#endif

-

-#if defined(STM32L4XX)

-    if ((clkmask & 0x7) == 0) {

-      rccDisableADC123();

+      adcp->adcc->CCR = STM32_ADC_ADC3_CLOCK_MODE | ADC_DMA_DAMDF;

+      rccDisableADC3();

     }

 #endif

   }

@@ -796,38 +497,35 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
 

   /* Calculating control registers values.*/

   dmamode = adcp->dmamode;

-  cfgr    = grpp->cfgr | ADC_CFGR_DMAEN;

   if (grpp->circular) {

     dmamode |= STM32_DMA_CR_CIRC;

-#if STM32_ADC_DUAL_MODE

-    ccr  |= ADC_CCR_DMACFG_CIRCULAR;

-#else

-    cfgr |= ADC_CFGR_DMACFG_CIRCULAR;

-#endif

+    cfgr = grpp->cfgr | ADC_CFGR_DMNGT_CIRCULAR;

     if (adcp->depth > 1) {

       /* If circular buffer depth > 1, then the half transfer interrupt

          is enabled in order to allow streaming processing.*/

       dmamode |= STM32_DMA_CR_HTIE;

     }

+    else {

+      cfgr = grpp->cfgr | ADC_CFGR_DMNGT_ONESHOT;

+    }

   }

 

   /* DMA setup.*/

-  dmaStreamSetMemory0(adcp->dmastp, adcp->samples);

+  dmaStreamSetMemory0(adcp->data.dma, adcp->samples);

 #if STM32_ADC_DUAL_MODE

-  dmaStreamSetTransactionSize(adcp->dmastp, ((uint32_t)grpp->num_channels/2) *

-                                            (uint32_t)adcp->depth);

+  dmaStreamSetTransactionSize(adcp->data.dma, ((uint32_t)grpp->num_channels / 2U) *

+                                              (uint32_t)adcp->depth);

 #else

-  dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *

-                                            (uint32_t)adcp->depth);

+  dmaStreamSetTransactionSize(adcp->data.dma, (uint32_t)grpp->num_channels *

+                                              (uint32_t)adcp->depth);

 #endif

-  dmaStreamSetMode(adcp->dmastp, dmamode);

-  dmaStreamEnable(adcp->dmastp);

+  dmaStreamSetMode(adcp->data.dma, dmamode);

+  dmaStreamEnable(adcp->data.dma);

 

   /* ADC setup, if it is defined a callback for the analog watch dog then it

      is enabled.*/

   adcp->adcm->ISR   = adcp->adcm->ISR;

   adcp->adcm->IER   = ADC_IER_OVR | ADC_IER_AWD1;

-  adcp->adcm->TR1   = grpp->tr1;

 #if STM32_ADC_DUAL_MODE

 

   /* Configuring the CCR register with the user-specified settings

@@ -836,12 +534,26 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
   adcp->adcc->CCR   = (adcp->adcc->CCR &

                        (ADC_CCR_CKMODE_MASK | ADC_CCR_MDMA_MASK)) | ccr;

 

+  adcp->adcm->PCSEL = grpp->pcsel;

+  adcp->adcm->LTR1  = grpp->ltr1;

+  adcp->adcm->HTR1  = grpp->htr1;

+  adcp->adcm->LTR1  = grpp->ltr2;

+  adcp->adcm->HTR1  = grpp->htr2;

+  adcp->adcm->LTR1  = grpp->ltr3;

+  adcp->adcm->HTR1  = grpp->htr3;

   adcp->adcm->SMPR1 = grpp->smpr[0];

   adcp->adcm->SMPR2 = grpp->smpr[1];

   adcp->adcm->SQR1  = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);

   adcp->adcm->SQR2  = grpp->sqr[1];

   adcp->adcm->SQR3  = grpp->sqr[2];

   adcp->adcm->SQR4  = grpp->sqr[3];

+  adcp->adcs->PCSEL = grpp->spcsel;

+  adcp->adcs->LTR1  = grpp->sltr1;

+  adcp->adcs->HTR1  = grpp->shtr1;

+  adcp->adcs->LTR1  = grpp->sltr2;

+  adcp->adcs->HTR1  = grpp->shtr2;

+  adcp->adcs->LTR1  = grpp->sltr3;

+  adcp->adcs->HTR1  = grpp->shtr3;

   adcp->adcs->SMPR1 = grpp->ssmpr[0];

   adcp->adcs->SMPR2 = grpp->ssmpr[1];

   adcp->adcs->SQR1  = grpp->ssqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);

@@ -850,6 +562,13 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
   adcp->adcs->SQR4  = grpp->ssqr[3];

 

 #else /* !STM32_ADC_DUAL_MODE */

+  adcp->adcm->PCSEL = grpp->pcsel;

+  adcp->adcm->LTR1  = grpp->ltr1;

+  adcp->adcm->HTR1  = grpp->htr1;

+  adcp->adcm->LTR1  = grpp->ltr2;

+  adcp->adcm->HTR1  = grpp->htr2;

+  adcp->adcm->LTR1  = grpp->ltr3;

+  adcp->adcm->HTR1  = grpp->htr3;

   adcp->adcm->SMPR1 = grpp->smpr[0];

   adcp->adcm->SMPR2 = grpp->smpr[1];

   adcp->adcm->SQR1  = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels);

@@ -874,7 +593,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
  */

 void adc_lld_stop_conversion(ADCDriver *adcp) {

 

-  dmaStreamDisable(adcp->dmastp);

+  dmaStreamDisable(adcp->data.dma);

   adc_lld_stop_adc(adcp);

 }

 

diff --git a/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h b/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h
index 8bffe3f79..b2d788d2c 100644
--- a/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h
+++ b/os/hal/ports/STM32/LLD/ADCv4/hal_adc_lld.h
@@ -114,6 +114,10 @@
 #define ADC_CCR_DUAL_FIELD(n)           ((n) << 0U)

 #define ADC_CCR_DELAY_MASK              (15U << 8U)

 #define ADC_CCR_DELAY_FIELD(n)          ((n) << 8U)

+#define ADC_CCR_DAMDF_MASK              (3U << 14U)

+#define ADC_CCR_DAMDF_DISABLED          (0U << 14U)

+#define ADC_CCR_DAMDF_HWORD             (2U << 14U)

+#define ADC_CCR_DAMDF_WORD              (3U << 14U)

 #define ADC_CCR_CKMODE_MASK             (3U << 16U)

 #define ADC_CCR_CKMODE_ADCCK            (0U << 16U)

 #define ADC_CCR_CKMODE_AHB_DIV1         (1U << 16U)

@@ -130,8 +134,7 @@
  * @{

  */

 /**

- * @brief   Enables the ADC master/slave mode.

- * @note    In dual mode only ADCD1 and ADCD3 are available.

+ * @brief   Enables the ADC1 and ADC2 master/slave mode.

  */

 #if !defined(STM32_ADC_DUAL_MODE) || defined(__DOXYGEN__)

 #define STM32_ADC_DUAL_MODE                 FALSE

@@ -139,29 +142,20 @@
 

 /**

  * @brief   Makes the ADC samples type an 8bits one.

- * @note    10 and 12 bits sampling mode must not be used when this option

- *          is enabled.

+ * @note    10, 12, 14 and 16 bits sampling mode must not be used when this

+ *          option is enabled.

  */

 #if !defined(STM32_ADC_COMPACT_SAMPLES) || defined(__DOXYGEN__)

 #define STM32_ADC_COMPACT_SAMPLES           FALSE

 #endif

 

 /**

- * @brief   ADC1 driver enable switch.

- * @details If set to @p TRUE the support for ADC1 is included.

+ * @brief   ADC1/ADC2 driver enable switch.

+ * @details If set to @p TRUE the support for ADC1/ADC2 is included.

  * @note    The default is @p FALSE.

  */

-#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)

-#define STM32_ADC_USE_ADC1                  FALSE

-#endif

-

-/**

- * @brief   ADC2 driver enable switch.

- * @details If set to @p TRUE the support for ADC2 is included.

- * @note    The default is @p FALSE.

- */

-#if !defined(STM32_ADC_USE_ADC2) || defined(__DOXYGEN__)

-#define STM32_ADC_USE_ADC2                  FALSE

+#if !defined(STM32_ADC_USE_ADC12) || defined(__DOXYGEN__)

+#define STM32_ADC_USE_ADC12                 FALSE

 #endif

 

 /**

@@ -172,27 +166,26 @@
 #if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__)

 #define STM32_ADC_USE_ADC3                  FALSE

 #endif

+

 /**

- * @brief   ADC4 driver enable switch.

- * @details If set to @p TRUE the support for ADC4 is included.

- * @note    The default is @p FALSE.

+ * @brief   ADC1/ADC2 DMA channel.

  */

-#if !defined(STM32_ADC_USE_ADC4) || defined(__DOXYGEN__)

-#define STM32_ADC_USE_ADC4                  FALSE

+#if !defined(STM32_ADC_ADC12_DMA_CHANNEL) || defined(__DOXYGEN__)

+#define STM32_ADC_ADC12_DMA_CHANNEL         0

 #endif

 

 /**

- * @brief   ADC1 DMA priority (0..3|lowest..highest).

+ * @brief   ADC3 DMA channel.

  */

-#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_ADC_ADC1_DMA_PRIORITY         2

+#if !defined(STM32_ADC_ADC3_DMA_CHANNEL) || defined(__DOXYGEN__)

+#define STM32_ADC_ADC3_DMA_CHANNEL          1

 #endif

 

 /**

- * @brief   ADC2 DMA priority (0..3|lowest..highest).

+ * @brief   ADC1/ADC2 DMA priority (0..3|lowest..highest).

  */

-#if !defined(STM32_ADC_ADC2_DMA_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_ADC_ADC2_DMA_PRIORITY         2

+#if !defined(STM32_ADC_ADC12_DMA_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_ADC_ADC12_DMA_PRIORITY        2

 #endif

 

 /**

@@ -203,13 +196,6 @@
 #endif

 

 /**

- * @brief   ADC4 DMA priority (0..3|lowest..highest).

- */

-#if !defined(STM32_ADC_ADC4_DMA_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_ADC_ADC4_DMA_PRIORITY         2

-#endif

-

-/**

  * @brief   ADC1/ADC2 interrupt priority level setting.

  */

 #if !defined(STM32_ADC_ADC12_IRQ_PRIORITY) || defined(__DOXYGEN__)

@@ -224,41 +210,6 @@
 #endif

 

 /**

- * @brief   ADC4 interrupt priority level setting.

- */

-#if !defined(STM32_ADC_ADC4_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_ADC_ADC4_IRQ_PRIORITY         5

-#endif

-

-/**

- * @brief   ADC1 DMA interrupt priority level setting.

- */

-#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5

-#endif

-

-/**

- * @brief   ADC2 DMA interrupt priority level setting.

- */

-#if !defined(STM32_ADC_ADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5

-#endif

-

-/**

- * @brief   ADC3 DMA interrupt priority level setting.

- */

-#if !defined(STM32_ADC_ADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5

-#endif

-

-/**

- * @brief   ADC4 DMA interrupt priority level setting.

- */

-#if !defined(STM32_ADC_ADC4_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY     5

-#endif

-

-/**

  * @brief   ADC1/ADC2 clock source and mode.

  */

 #if !defined(STM32_ADC_ADC12_CLOCK_MODE) || defined(__DOXYGEN__)

@@ -266,12 +217,11 @@
 #endif

 

 /**

- * @brief   ADC3/ADC4 clock source and mode.

+ * @brief   ADC3 clock source and mode.

  */

-#if !defined(STM32_ADC_ADC34_CLOCK_MODE) || defined(__DOXYGEN__)

-#define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV4

+#if !defined(STM32_ADC_ADC3_CLOCK_MODE) || defined(__DOXYGEN__)

+#define STM32_ADC_ADC3_CLOCK_MODE           ADC_CCR_CKMODE_AHB_DIV4

 #endif

-

 /** @} */

 

 /*===========================================================================*/

@@ -285,16 +235,16 @@
 

 /* Registry checks.*/

 #if !defined(STM32_HAS_ADC1) || !defined(STM32_HAS_ADC2) ||                 \

-    !defined(STM32_HAS_ADC3) || !defined(STM32_HAS_ADC4)

+    !defined(STM32_HAS_ADC3)

 #error "STM32_ADC_USE_ADCx not defined in registry"

 #endif

 

 /* Units checks.*/

-#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1

+#if STM32_ADC_USE_ADC12 && !STM32_HAS_ADC1

 #error "ADC1 not present in the selected device"

 #endif

 

-#if STM32_ADC_USE_ADC2 && !STM32_HAS_ADC2

+#if STM32_ADC_DUAL_MODE && !STM32_HAS_ADC2

 #error "ADC2 not present in the selected device"

 #endif

 

@@ -302,42 +252,30 @@
 #error "ADC3 not present in the selected device"

 #endif

 

-#if STM32_ADC_USE_ADC4 && !STM32_HAS_ADC4

-#error "ADC4 not present in the selected device"

-#endif

-

 /* IRQ handlers checks.*/

 #if STM32_HAS_ADC1 && !defined(STM32_ADC12_HANDLER)

-#error "STM32_ADCx_HANDLER not defined in registry"

+#error "STM32_ADC12_HANDLER not defined in registry"

 #endif

 

 #if STM32_HAS_ADC2 && !defined(STM32_ADC12_HANDLER)

-#error "STM32_ADCx_HANDLER not defined in registry"

-#endif

-

-#if STM32_HAS_ADC3 && !defined(STM32_ADC34_HANDLER)

-#error "STM32_ADCx_HANDLER not defined in registry"

+#error "STM32_ADC12_HANDLER not defined in registry"

 #endif

 

-#if STM32_HAS_ADC4 && !defined(STM32_ADC34_HANDLER)

-#error "STM32_ADCx_HANDLER not defined in registry"

+#if STM32_HAS_ADC3 && !defined(STM32_ADC3_HANDLER)

+#error "STM32_ADC3_HANDLER not defined in registry"

 #endif

 

 /* IRQ vector numbers checks.*/

 #if STM32_HAS_ADC1 && !defined(STM32_ADC12_NUMBER)

-#error "STM32_ADCx_NUMBER not defined in registry"

+#error "STM32_ADC12_NUMBER not defined in registry"

 #endif

 

 #if STM32_HAS_ADC2 && !defined(STM32_ADC12_NUMBER)

-#error "STM32_ADCx_NUMBER not defined in registry"

+#error "STM32_ADC12_NUMBER not defined in registry"

 #endif

 

-#if STM32_HAS_ADC3 && !defined(STM32_ADC34_NUMBER)

-#error "STM32_ADCx_NUMBER not defined in registry"

-#endif

-

-#if STM32_HAS_ADC4 && !defined(STM32_ADC34_NUMBER)

-#error "STM32_ADCx_NUMBER not defined in registry"

+#if STM32_HAS_ADC3 && !defined(STM32_ADC3_NUMBER)

+#error "STM32_ADC3_NUMBER not defined in registry"

 #endif

 

 /* Units checks related to dual mode.*/

@@ -345,85 +283,42 @@
 #error "ADC2 not present in the selected device, required for dual mode"

 #endif

 

-#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC3 && !STM32_HAS_ADC4

-#error "ADC4 not present in the selected device, required for dual mode"

-#endif

-

-#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC2

-#error "ADC2 cannot be used in dual mode"

-#endif

-

-#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC4

-#error "ADC4 cannot be used in dual mode"

-#endif

-

 /* At least one ADC must be assigned.*/

-#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 &&                           \

-    !STM32_ADC_USE_ADC3 && !STM32_ADC_USE_ADC4

+#if !STM32_ADC_USE_ADC12 && !STM32_ADC_USE_ADC3

 #error "ADC driver activated but no ADC peripheral assigned"

 #endif

 

-/* ADC IRQ priority tests.*/

-#if STM32_ADC_USE_ADC1 &&                                                   \

-    !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY)

-#error "Invalid IRQ priority assigned to ADC1"

-#endif

-

-#if STM32_ADC_USE_ADC2 &&                                                   \

-    !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY)

-#error "Invalid IRQ priority assigned to ADC2"

+/* DMA channel range tests.*/

+#if STM32_ADC_USE_ADC12 &&                                                  \

+    !STM32_DMA_IS_VALID_CHANNEL(STM32_ADC_ADC12_DMA_CHANNEL)

+#error "Invalid DMA channel assigned to ADC12"

 #endif

 

 #if STM32_ADC_USE_ADC3 &&                                                   \

-    !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC34_IRQ_PRIORITY)

-#error "Invalid IRQ priority assigned to ADC3"

-#endif

-

-#if STM32_ADC_USE_ADC4 &&                                                   \

-    !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC34_IRQ_PRIORITY)

-#error "Invalid IRQ priority assigned to ADC4"

-#endif

-

-/* DMA IRQ priority tests.*/

-#if STM32_ADC_USE_ADC1 &&                                                   \

-    !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)

-#error "Invalid IRQ priority assigned to ADC1 DMA"

-#endif

-

-#if STM32_ADC_USE_ADC2 &&                                                   \

-    !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC2_DMA_IRQ_PRIORITY)

-#error "Invalid IRQ priority assigned to ADC2 DMA"

-#endif

-

-#if STM32_ADC_USE_ADC3 &&                                                   \

-    !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC3_DMA_IRQ_PRIORITY)

-#error "Invalid IRQ priority assigned to ADC3 DMA"

-#endif

-

-#if STM32_ADC_USE_ADC4 &&                                                   \

-    !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC4_DMA_IRQ_PRIORITY)

-#error "Invalid IRQ priority assigned to ADC4 DMA"

+    !STM32_BDMA_IS_VALID_CHANNEL(STM32_ADC_ADC3_DMA_CHANNEL)

+#error "Invalid DMA channel assigned to ADC3"

 #endif

 

 /* DMA priority tests.*/

-#if STM32_ADC_USE_ADC1 &&                                                   \

-    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)

+#if STM32_ADC_USE_ADC12 &&                                                  \

+    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC12_DMA_PRIORITY)

 #error "Invalid DMA priority assigned to ADC1"

 #endif

 

-#if STM32_ADC_USE_ADC2 &&                                                   \

-    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC2_DMA_PRIORITY)

-#error "Invalid DMA priority assigned to ADC2"

-#endif

-

 #if STM32_ADC_USE_ADC3 &&                                                   \

     !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC3_DMA_PRIORITY)

 #error "Invalid DMA priority assigned to ADC3"

 #endif

 

-#if STM32_ADC_USE_ADC4 &&                                                   \

-    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC4_DMA_PRIORITY)

-#error "Invalid DMA priority assigned to ADC4"

+/* ADC IRQ priority tests.*/

+#if STM32_ADC_USE_ADC12 &&                                                  \

+    !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY)

+#error "Invalid IRQ priority assigned to ADC1"

+#endif

+

+#if STM32_ADC_USE_ADC3 &&                                                   \

+    !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC34_IRQ_PRIORITY)

+#error "Invalid IRQ priority assigned to ADC3"

 #endif

 

 /* ADC clock source checks.*/

@@ -439,29 +334,43 @@
 #error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"

 #endif

 

-#if STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK

-#define STM32_ADC34_CLOCK               STM32_ADCCLK

-#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1

-#define STM32_ADC34_CLOCK               (STM32_HCLK / 1)

-#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2

-#define STM32_ADC34_CLOCK               (STM32_HCLK / 2)

-#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4

-#define STM32_ADC34_CLOCK               (STM32_HCLK / 4)

+#if STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK

+#define STM32_ADC3_CLOCK                STM32_ADCCLK

+#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1

+#define STM32_ADC3_CLOCK                (STM32_HCLK / 1)

+#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2

+#define STM32_ADC3_CLOCK                (STM32_HCLK / 2)

+#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4

+#define STM32_ADC3_CLOCK                (STM32_HCLK / 4)

 #else

-#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"

+#error "invalid clock mode selected for STM32_ADC_ADC3_CLOCK_MODE"

 #endif

 

 #if STM32_ADC12_CLOCK > STM32_ADCCLK_MAX

 #error "STM32_ADC12_CLOCK exceeding maximum frequency (STM32_ADCCLK_MAX)"

 #endif

 

-#if STM32_ADC34_CLOCK > STM32_ADCCLK_MAX

-#error "STM32_ADC34_CLOCK exceeding maximum frequency (STM32_ADCCLK_MAX)"

+#if STM32_ADC3_CLOCK > STM32_ADCCLK_MAX

+#error "STM32_ADC3_CLOCK exceeding maximum frequency (STM32_ADCCLK_MAX)"

+#endif

+

+#if !defined(STM32_DMA_REQUIRED)

+#define STM32_DMA_REQUIRED

 #endif

 

+#if STM32_ADC_USE_ADC12

+#define STM32_ADC_DMA_REQUIRED

 #if !defined(STM32_DMA_REQUIRED)

 #define STM32_DMA_REQUIRED

 #endif

+#endif

+

+#if STM32_ADC_USE_ADC3

+#define STM32_ADC_BDMA_REQUIRED

+#if !defined(STM32_BDMA_REQUIRED)

+#define STM32_BDMA_REQUIRED

+#endif

+#endif

 

 /*===========================================================================*/

 /* Driver data structures and types.                                         */

@@ -479,7 +388,7 @@ typedef uint8_t adcsample_t;
 /**

  * @brief   Channels number in a conversion group.

  */

-typedef uint16_t adc_channels_num_t;

+typedef uint32_t adc_channels_num_t;

 

 /**

  * @brief   Possible ADC failure causes.

@@ -546,27 +455,51 @@ typedef struct {
   /* End of the mandatory fields.*/

   /**

    * @brief   ADC CFGR register initialization data.

-   * @note    The bits DMAEN and DMACFG are enforced internally

-   *          to the driver, keep them to zero.

+   * @note    The bits DMNGT are enforced internally to the driver, keep

+   *          them to zero.

    * @note    The bits @p ADC_CFGR_CONT or @p ADC_CFGR_DISCEN must be

    *          specified in continuous mode or if the buffer depth is

    *          greater than one.

    */

   uint32_t                  cfgr;

-  /**

-   * @brief   ADC TR1 register initialization data.

-   */

-  uint32_t                  tr1;

 #if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)

   /**

    * @brief   ADC CCR register initialization data.

-   * @note    The bits CKMODE, MDMA, DMACFG are enforced internally to the

+   * @note    The bits CKMODE and DAMDF are enforced internally to the

    *          driver, keep them to zero.

    * @note    This field is only present in dual mode.

    */

   uint32_t                  ccr;

 #endif

   /**

+   * @brief   ADC PCSEL register initialization data.

+   */

+  uint32_t                  pcsel;

+  /**

+   * @brief   ADC LTR1 register initialization data.

+   */

+  uint32_t                  ltr1;

+  /**

+   * @brief   ADC HTR1 register initialization data.

+   */

+  uint32_t                  htr1;

+  /**

+   * @brief   ADC LTR2 register initialization data.

+   */

+  uint32_t                  ltr2;

+  /**

+   * @brief   ADC HTR2 register initialization data.

+   */

+  uint32_t                  htr2;

+  /**

+   * @brief   ADC LTR3 register initialization data.

+   */

+  uint32_t                  ltr3;

+  /**

+   * @brief   ADC HTR3 register initialization data.

+   */

+  uint32_t                  htr3;

+  /**

    * @brief   ADC SMPRx registers initialization data.

    */

   uint32_t                  smpr[2];

@@ -576,6 +509,34 @@ typedef struct {
   uint32_t                  sqr[4];

 #if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)

   /**

+   * @brief   Slave ADC PCSEL register initialization data.

+   */

+  uint32_t                  spcsel;

+  /**

+   * @brief   Slave ADC LTR1 register initialization data.

+   */

+  uint32_t                  sltr1;

+  /**

+   * @brief   Slave ADC HTR1 register initialization data.

+   */

+  uint32_t                  shtr1;

+  /**

+   * @brief   Slave ADC LTR2 register initialization data.

+   */

+  uint32_t                  sltr2;

+  /**

+   * @brief   Slave ADC HTR2 register initialization data.

+   */

+  uint32_t                  shtr2;

+  /**

+   * @brief   Slave ADC LTR3 register initialization data.

+   */

+  uint32_t                  sltr3;

+  /**

+   * @brief   Slave ADC HTR3 register initialization data.

+   */

+  uint32_t                  shtr3;

+  /**

    * @brief   Slave ADC SMPRx registers initialization data.

    * @note    This field is only present in dual mode.

    */

@@ -653,9 +614,22 @@ struct ADCDriver {
    */

   ADC_Common_TypeDef        *adcc;

   /**

-   * @brief   Pointer to associated DMA channel.

+   * @brief   Union of the DMA data streams.

    */

-  const stm32_dma_stream_t  *dmastp;

+  union {

+#if defined(STM32_ADC_DMA_REQUIRED) || defined(__DOXYGEN__)

+    /**

+     * @brief   DMA stream.

+     */

+    const stm32_dma_stream_t  *dma;

+#endif

+#if defined(STM32_ADC_BDMA_REQUIRED) || defined(__DOXYGEN__)

+    /**

+     * @brief   BDMA stream.

+     */

+    const stm32_bdma_stream_t  *bdma;

+#endif

+  } data;

   /**

    * @brief   DMA mode bit mask.

    */

@@ -667,88 +641,74 @@ struct ADCDriver {
 /*===========================================================================*/

 

 /**

- * @name    Threashold register initializer

- * @{

- */

-#define ADC_TR(low, high)       (((uint32_t)(high) << 16) | (uint32_t)(low))

-/** @} */

-

-/**

  * @name    Sequences building helper macros

  * @{

  */

 /**

  * @brief   Number of channels in a conversion sequence.

  */

-#define ADC_SQR1_NUM_CH(n)      (((n) - 1) << 0)

-

-#define ADC_SQR1_SQ1_N(n)       ((n) << 6)  /**< @brief 1st channel in seq. */

-#define ADC_SQR1_SQ2_N(n)       ((n) << 12) /**< @brief 2nd channel in seq. */

-#define ADC_SQR1_SQ3_N(n)       ((n) << 18) /**< @brief 3rd channel in seq. */

-#define ADC_SQR1_SQ4_N(n)       ((n) << 24) /**< @brief 4th channel in seq. */

-

-#define ADC_SQR2_SQ5_N(n)       ((n) << 0)  /**< @brief 5th channel in seq. */

-#define ADC_SQR2_SQ6_N(n)       ((n) << 6)  /**< @brief 6th channel in seq. */

-#define ADC_SQR2_SQ7_N(n)       ((n) << 12) /**< @brief 7th channel in seq. */

-#define ADC_SQR2_SQ8_N(n)       ((n) << 18) /**< @brief 8th channel in seq. */

-#define ADC_SQR2_SQ9_N(n)       ((n) << 24) /**< @brief 9th channel in seq. */

-

-#define ADC_SQR3_SQ10_N(n)      ((n) << 0)  /**< @brief 10th channel in seq.*/

-#define ADC_SQR3_SQ11_N(n)      ((n) << 6)  /**< @brief 11th channel in seq.*/

-#define ADC_SQR3_SQ12_N(n)      ((n) << 12) /**< @brief 12th channel in seq.*/

-#define ADC_SQR3_SQ13_N(n)      ((n) << 18) /**< @brief 13th channel in seq.*/

-#define ADC_SQR3_SQ14_N(n)      ((n) << 24) /**< @brief 14th channel in seq.*/

-

-#define ADC_SQR4_SQ15_N(n)      ((n) << 0)  /**< @brief 15th channel in seq.*/

-#define ADC_SQR4_SQ16_N(n)      ((n) << 6)  /**< @brief 16th channel in seq.*/

+#define ADC_SQR1_NUM_CH(n)      (((n) - 1U) << 0U)

+

+#define ADC_SQR1_SQ1_N(n)       ((n) << 6U) /**< @brief 1st channel in seq. */

+#define ADC_SQR1_SQ2_N(n)       ((n) << 12U)/**< @brief 2nd channel in seq. */

+#define ADC_SQR1_SQ3_N(n)       ((n) << 18U)/**< @brief 3rd channel in seq. */

+#define ADC_SQR1_SQ4_N(n)       ((n) << 24U)/**< @brief 4th channel in seq. */

+

+#define ADC_SQR2_SQ5_N(n)       ((n) << 0U) /**< @brief 5th channel in seq. */

+#define ADC_SQR2_SQ6_N(n)       ((n) << 6U) /**< @brief 6th channel in seq. */

+#define ADC_SQR2_SQ7_N(n)       ((n) << 12U)/**< @brief 7th channel in seq. */

+#define ADC_SQR2_SQ8_N(n)       ((n) << 18U)/**< @brief 8th channel in seq. */

+#define ADC_SQR2_SQ9_N(n)       ((n) << 24U)/**< @brief 9th channel in seq. */

+

+#define ADC_SQR3_SQ10_N(n)      ((n) << 0U) /**< @brief 10th channel in seq.*/

+#define ADC_SQR3_SQ11_N(n)      ((n) << 6U) /**< @brief 11th channel in seq.*/

+#define ADC_SQR3_SQ12_N(n)      ((n) << 12U)/**< @brief 12th channel in seq.*/

+#define ADC_SQR3_SQ13_N(n)      ((n) << 18U)/**< @brief 13th channel in seq.*/

+#define ADC_SQR3_SQ14_N(n)      ((n) << 24U)/**< @brief 14th channel in seq.*/

+

+#define ADC_SQR4_SQ15_N(n)      ((n) << 0U) /**< @brief 15th channel in seq.*/

+#define ADC_SQR4_SQ16_N(n)      ((n) << 6U) /**< @brief 16th channel in seq.*/

 /** @} */

 

 /**

  * @name    Sampling rate settings helper macros

  * @{

  */

-#define ADC_SMPR1_SMP_AN0(n)    ((n) << 0)  /**< @brief AN0 sampling time.  */

-#define ADC_SMPR1_SMP_AN1(n)    ((n) << 3)  /**< @brief AN1 sampling time.  */

-#define ADC_SMPR1_SMP_AN2(n)    ((n) << 6)  /**< @brief AN2 sampling time.  */

-#define ADC_SMPR1_SMP_AN3(n)    ((n) << 9)  /**< @brief AN3 sampling time.  */

-#define ADC_SMPR1_SMP_AN4(n)    ((n) << 12) /**< @brief AN4 sampling time.  */

-#define ADC_SMPR1_SMP_AN5(n)    ((n) << 15) /**< @brief AN5 sampling time.  */

-#define ADC_SMPR1_SMP_AN6(n)    ((n) << 18) /**< @brief AN6 sampling time.  */

-#define ADC_SMPR1_SMP_AN7(n)    ((n) << 21) /**< @brief AN7 sampling time.  */

-#define ADC_SMPR1_SMP_AN8(n)    ((n) << 24) /**< @brief AN8 sampling time.  */

-#define ADC_SMPR1_SMP_AN9(n)    ((n) << 27) /**< @brief AN9 sampling time.  */

-

-#define ADC_SMPR2_SMP_AN10(n)   ((n) << 0)  /**< @brief AN10 sampling time. */

-#define ADC_SMPR2_SMP_AN11(n)   ((n) << 3)  /**< @brief AN11 sampling time. */

-#define ADC_SMPR2_SMP_AN12(n)   ((n) << 6)  /**< @brief AN12 sampling time. */

-#define ADC_SMPR2_SMP_AN13(n)   ((n) << 9)  /**< @brief AN13 sampling time. */

-#define ADC_SMPR2_SMP_AN14(n)   ((n) << 12) /**< @brief AN14 sampling time. */

-#define ADC_SMPR2_SMP_AN15(n)   ((n) << 15) /**< @brief AN15 sampling time. */

-#define ADC_SMPR2_SMP_AN16(n)   ((n) << 18) /**< @brief AN16 sampling time. */

-#define ADC_SMPR2_SMP_AN17(n)   ((n) << 21) /**< @brief AN17 sampling time. */

-#define ADC_SMPR2_SMP_AN18(n)   ((n) << 24) /**< @brief AN18 sampling time. */

+#define ADC_SMPR1_SMP_AN0(n)    ((n) << 0U) /**< @brief AN0 sampling time.  */

+#define ADC_SMPR1_SMP_AN1(n)    ((n) << 3U) /**< @brief AN1 sampling time.  */

+#define ADC_SMPR1_SMP_AN2(n)    ((n) << 6U) /**< @brief AN2 sampling time.  */

+#define ADC_SMPR1_SMP_AN3(n)    ((n) << 9U) /**< @brief AN3 sampling time.  */

+#define ADC_SMPR1_SMP_AN4(n)    ((n) << 12U)/**< @brief AN4 sampling time.  */

+#define ADC_SMPR1_SMP_AN5(n)    ((n) << 15U)/**< @brief AN5 sampling time.  */

+#define ADC_SMPR1_SMP_AN6(n)    ((n) << 18U)/**< @brief AN6 sampling time.  */

+#define ADC_SMPR1_SMP_AN7(n)    ((n) << 21U)/**< @brief AN7 sampling time.  */

+#define ADC_SMPR1_SMP_AN8(n)    ((n) << 24U)/**< @brief AN8 sampling time.  */

+#define ADC_SMPR1_SMP_AN9(n)    ((n) << 27U)/**< @brief AN9 sampling time.  */

+

+#define ADC_SMPR2_SMP_AN10(n)   ((n) << 0U) /**< @brief AN10 sampling time. */

+#define ADC_SMPR2_SMP_AN11(n)   ((n) << 3U) /**< @brief AN11 sampling time. */

+#define ADC_SMPR2_SMP_AN12(n)   ((n) << 6U) /**< @brief AN12 sampling time. */

+#define ADC_SMPR2_SMP_AN13(n)   ((n) << 9U) /**< @brief AN13 sampling time. */

+#define ADC_SMPR2_SMP_AN14(n)   ((n) << 12U)/**< @brief AN14 sampling time. */

+#define ADC_SMPR2_SMP_AN15(n)   ((n) << 15U)/**< @brief AN15 sampling time. */

+#define ADC_SMPR2_SMP_AN16(n)   ((n) << 18U)/**< @brief AN16 sampling time. */

+#define ADC_SMPR2_SMP_AN17(n)   ((n) << 21U)/**< @brief AN17 sampling time. */

+#define ADC_SMPR2_SMP_AN18(n)   ((n) << 24U)/**< @brief AN18 sampling time. */

+#define ADC_SMPR2_SMP_AN19(n)   ((n) << 27U)/**< @brief AN19 sampling time. */

 /** @} */

 

 /*===========================================================================*/

 /* External declarations.                                                    */

 /*===========================================================================*/

 

-#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)

+#if STM32_ADC_USE_ADC12 && !defined(__DOXYGEN__)

 extern ADCDriver ADCD1;

 #endif

 

-#if STM32_ADC_USE_ADC2 && !defined(__DOXYGEN__)

-extern ADCDriver ADCD2;

-#endif

-

 #if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__)

 extern ADCDriver ADCD3;

 #endif

 

-#if STM32_ADC_USE_ADC4 && !defined(__DOXYGEN__)

-extern ADCDriver ADCD4;

-#endif

-

 #ifdef __cplusplus

 extern "C" {

 #endif