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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-01-03 10:47:31 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-01-03 10:47:31 +0000 |
| commit | 06cdcc071c82cd139b18e21648a8f559cc07fa98 (patch) | |
| tree | 36685a32ab372e59370bedea79506817c9bbccf5 /os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.h | |
| parent | 84e0ad64f09f16ae8fa37f9221bd292044a7325f (diff) | |
| download | ChibiOS-06cdcc071c82cd139b18e21648a8f559cc07fa98.tar.gz ChibiOS-06cdcc071c82cd139b18e21648a8f559cc07fa98.tar.bz2 ChibiOS-06cdcc071c82cd139b18e21648a8f559cc07fa98.zip | |
More work on STM32 SPIv3 and DMAv3 drivers, to be tested.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11215 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.h')
| -rw-r--r-- | os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.h | 144 |
1 files changed, 144 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.h b/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.h index ab267ab49..75ee4f097 100644 --- a/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.h +++ b/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.h @@ -143,6 +143,90 @@ #endif
/**
+ * @brief SPI1 RX DMA channel setting.
+ */
+#if !defined(STM32_SPI_SPI1_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI1_RX_DMA_CHANNEL 10
+#endif
+
+/**
+ * @brief SPI1 TX DMA channel setting.
+ */
+#if !defined(STM32_SPI_SPI1_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI1_TX_DMA_CHANNEL 11
+#endif
+
+/**
+ * @brief SPI2 RX DMA channel setting.
+ */
+#if !defined(STM32_SPI_SPI2_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI2_RX_DMA_CHANNEL 12
+#endif
+
+/**
+ * @brief SPI2 TX DMA channel setting.
+ */
+#if !defined(STM32_SPI_SPI2_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI2_TX_DMA_CHANNEL 13
+#endif
+
+/**
+ * @brief SPI3 RX DMA channel setting.
+ */
+#if !defined(STM32_SPI_SPI3_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI3_RX_DMA_CHANNEL 10
+#endif
+
+/**
+ * @brief SPI3 TX DMA channel setting.
+ */
+#if !defined(STM32_SPI_SPI3_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI3_TX_DMA_CHANNEL 11
+#endif
+
+/**
+ * @brief SPI4 RX DMA channel setting.
+ */
+#if !defined(STM32_SPI_SPI4_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI4_RX_DMA_CHANNEL 12
+#endif
+
+/**
+ * @brief SPI4 TX DMA channel setting.
+ */
+#if !defined(STM32_SPI_SPI4_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI4_TX_DMA_CHANNEL 13
+#endif
+
+/**
+ * @brief SPI5 RX DMA channel setting.
+ */
+#if !defined(STM32_SPI_SPI5_RX_DMA_CHANNEL) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI5_RX_DMA_CHANNEL 12
+#endif
+
+/**
+ * @brief SPI5 TX DMA channel setting.
+ */
+#if !defined(STM32_SPI_SPI5_TX_DMA_CHANNEL) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI5_TX_DMA_CHANNEL 13
+#endif
+
+/**
+ * @brief SPI6 RX DMA channel setting.
+ */
+#if !defined(STM32_SPI_SPI6_RX_BDMA_CHANNEL) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI6_RX_BDMA_CHANNEL 2
+#endif
+
+/**
+ * @brief SPI6 TX DMA channel setting.
+ */
+#if !defined(STM32_SPI_SPI6_TX_BDMA_CHANNEL) || defined(__DOXYGEN__)
+#define STM32_SPI_SPI6_TX_BDMA_CHANNEL 3
+#endif
+
+/**
* @brief SPI1 DMA priority (0..3|lowest..highest).
* @note The priority level is used for both the TX and RX DMA streams but
* because of the streams ordering the RX stream has always priority
@@ -274,6 +358,66 @@ #endif
#if STM32_SPI_USE_SPI1 && \
+ !STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI1_RX_DMA_CHANNEL)
+#error "Invalid DMA channel assigned to SPI1 RX"
+#endif
+
+#if STM32_SPI_USE_SPI1 && \
+ !STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI1_TX_DMA_CHANNEL)
+#error "Invalid DMA channel assigned to SPI1 TX"
+#endif
+
+#if STM32_SPI_USE_SPI2 && \
+ !STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI2_RX_DMA_CHANNEL)
+#error "Invalid DMA channel assigned to SPI2 RX"
+#endif
+
+#if STM32_SPI_USE_SPI2 && \
+ !STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI2_TX_DMA_CHANNEL)
+#error "Invalid DMA channel assigned to SPI2 TX"
+#endif
+
+#if STM32_SPI_USE_SPI3 && \
+ !STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI3_RX_DMA_CHANNEL)
+#error "Invalid DMA channel assigned to SPI3 RX"
+#endif
+
+#if STM32_SPI_USE_SPI3 && \
+ !STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI3_TX_DMA_CHANNEL)
+#error "Invalid DMA channel assigned to SPI3 TX"
+#endif
+
+#if STM32_SPI_USE_SPI4 && \
+ !STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI4_RX_DMA_CHANNEL)
+#error "Invalid DMA channel assigned to SPI4 RX"
+#endif
+
+#if STM32_SPI_USE_SPI4 && \
+ !STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI4_TX_DMA_CHANNEL)
+#error "Invalid DMA channel assigned to SPI4 TX"
+#endif
+
+#if STM32_SPI_USE_SPI5 && \
+ !STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI5_RX_DMA_CHANNEL)
+#error "Invalid DMA channel assigned to SPI5 RX"
+#endif
+
+#if STM32_SPI_USE_SPI5 && \
+ !STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI5_TX_DMA_CHANNEL)
+#error "Invalid DMA channel assigned to SPI5 TX"
+#endif
+
+#if STM32_SPI_USE_SPI6 && \
+ !STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI6_RX_BDMA_CHANNEL)
+#error "Invalid BDMA channel assigned to SPI6 RX"
+#endif
+
+#if STM32_SPI_USE_SPI6 && \
+ !STM32_DMA_IS_VALID_CHANNEL(STM32_SPI_SPI6_TX_BDMA_CHANNEL)
+#error "Invalid BDMA channel assigned to SPI1 TX"
+#endif
+
+#if STM32_SPI_USE_SPI1 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to SPI1"
#endif
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