SDMMC2 support, removed a duplicated comment in ADCv3.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9671 35acf78f-673a-0410-8e92-d51de3d6d3f4

1 files changed, 82 insertions, 8 deletions

diff --git a/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.h b/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.h
index 1b09d6862..4479a1c5b 100644
--- a/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.h
+++ b/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.h
@@ -40,7 +40,7 @@
  * @{

  */

 /**

- * @brief   SDMMC driver enable switch.

+ * @brief   SDMMC1 driver enable switch.

  * @details If set to @p TRUE the support for SDMMC1 is included.

  * @note    The default is @p FALSE.

  */

@@ -49,6 +49,15 @@
 #endif

 

 /**

+ * @brief   SDMMC2 driver enable switch.

+ * @details If set to @p TRUE the support for SDMMC2 is included.

+ * @note    The default is @p FALSE.

+ */

+#if !defined(STM32_SDC_USE_SDMMC2) || defined(__DOXYGEN__)

+#define STM32_SDC_USE_SDMMC2                FALSE

+#endif

+

+/**

  * @brief   Support for unaligned transfers.

  * @note    Unaligned transfers are much slower.

  */

@@ -85,25 +94,66 @@
 #endif

 

 /**

+ * @brief   SDMMC2 DMA priority (0..3|lowest..highest).

+ */

+#if !defined(STM32_SDC_SDMMC2_DMA_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_SDC_SDMMC2_DMA_PRIORITY       3

+#endif

+

+/**

  * @brief   SDMMC1 interrupt priority level setting.

  */

 #if !defined(STM32_SDC_SDMMC1_IRQ_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_SDC_SDMMC1_IRQ_PRIORITY       9

 #endif

+

+/**

+ * @brief   SDMMC2 interrupt priority level setting.

+ */

+#if !defined(STM32_SDC_SDMMC2_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_SDC_SDMMC2_IRQ_PRIORITY       9

+#endif

 /** @} */

 

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

+/* Registry checks.*/

+#if (STM32_SDC_USE_SDMMC1 && !defined(STM32_SDMMC1_HANDLER)) ||             \

+    (STM32_SDC_USE_SDMMC2 && !defined(STM32_SDMMC2_HANDLER))

+#error "STM32_SDMMCx_HANDLER not defined in registry"

+#endif

+

+#if (STM32_SDC_USE_SDMMC1 && !defined(STM32_SDMMC1_NUMBER)) ||              \

+    (STM32_SDC_USE_SDMMC2 && !defined(STM32_SDMMC2_NUMBER))

+#error "STM32_ADCx_NUMBER not defined in registry"

+#endif

+

+#if (STM32_SDC_USE_SDMMC1 && !defined(STM32_SDC_SDMMC1_DMA_MSK)) ||         \

+    (STM32_SDC_USE_SDMMC2 && !defined(STM32_SDC_SDMMC2_DMA_MSK))

+#error "STM32_SDC_SDMMCx_DMA_MSK not defined in registry"

+#endif

+

+#if (STM32_SDC_USE_SDMMC1 && !defined(STM32_SDC_SDMMC1_DMA_CHN)) ||         \

+    (STM32_SDC_USE_SDMMC2 && !defined(STM32_SDC_SDMMC2_DMA_CHN))

+#error "STM32_SDC_SDMMCx_DMA_CHN not defined in registry"

+#endif

+

+/* Units checks.*/

 #if STM32_SDC_USE_SDMMC1 && !STM32_HAS_SDMMC1

 #error "SDMMC1 not present in the selected device"

 #endif

 

-#if !STM32_SDC_USE_SDMMC1

+#if STM32_SDC_USE_SDMMC2 && !STM32_HAS_SDMMC2

+#error "SDMMC2 not present in the selected device"

+#endif

+

+#if !STM32_SDC_USE_SDMMC1 && !STM32_SDC_USE_SDMMC2

 #error "SDC driver activated but no SDMMC peripheral assigned"

 #endif

 

+/* Clock related tests.*/

 #if !defined(STM32_SDMMCCLK)

 #error "STM32_SDMMCCLK not defined"

 #endif

@@ -112,28 +162,48 @@
 #error "STM32_HCLK not defined"

 #endif

 

-#if STM32_SDC_USE_SDMMC1 * 10 > STM32_HCLK * 7

+#if STM32_SDMMCCLK * 10 > STM32_HCLK * 7

 #error "STM32_SDC_USE_SDMMC1 must not exceed STM32_HCLK * 0.7"

 #endif

 

+/* SDMMC IRQ priority tests.*/

 #if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SDC_SDMMC1_IRQ_PRIORITY)

-#error "Invalid IRQ priority assigned to SDIO"

+#error "Invalid IRQ priority assigned to SDMMC1"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SDC_SDMMC2_IRQ_PRIORITY)

+#error "Invalid IRQ priority assigned to SDMMC2"

 #endif

 

+/* DMA priority tests.*/

 #if !STM32_DMA_IS_VALID_PRIORITY(STM32_SDC_SDMMC1_DMA_PRIORITY)

-#error "Invalid DMA priority assigned to SDIO"

+#error "Invalid DMA priority assigned to SDMMC1"

+#endif

+

+#if !STM32_DMA_IS_VALID_PRIORITY(STM32_SDC_SDMMC2_DMA_PRIORITY)

+#error "Invalid DMA priority assigned to SDMMC2"

 #endif

 

 /* Check on the presence of the DMA streams settings in mcuconf.h.*/

-#if !defined(STM32_SDC_SDMMC1_DMA_STREAM)

+#if STM32_SDC_USE_SDMMC1 && !defined(STM32_SDC_SDMMC1_DMA_STREAM)

 #error "SDMMC1 DMA streams not defined"

 #endif

 

+#if STM32_SDC_USE_SDMMC2 && !defined(STM32_SDC_SDMMC2_DMA_STREAM)

+#error "SDMMC2 DMA streams not defined"

+#endif

+

 /* Check on the validity of the assigned DMA channels.*/

-#if !STM32_DMA_IS_VALID_ID(STM32_SDC_SDMMC1_DMA_STREAM, STM32_SDC_SDMMC1_DMA_MSK)

+#if STM32_SDC_USE_SDMMC1 &&                                                 \

+    !STM32_DMA_IS_VALID_ID(STM32_SDC_SDMMC1_DMA_STREAM, STM32_SDC_SDMMC1_DMA_MSK)

 #error "invalid DMA stream associated to SDMMC1"

 #endif

 

+#if STM32_SDC_USE_SDMMC2 &&                                                 \

+    !STM32_DMA_IS_VALID_ID(STM32_SDC_SDMMC2_DMA_STREAM, STM32_SDC_SDMMC2_DMA_MSK)

+#error "invalid DMA stream associated to SDMMC2"

+#endif

+

 #if !defined(STM32_DMA_REQUIRED)

 #define STM32_DMA_REQUIRED

 #endif

@@ -246,10 +316,14 @@ struct SDCDriver {
 /* External declarations.                                                    */

 /*===========================================================================*/

 

-#if !defined(__DOXYGEN__)

+#if STM32_SDC_USE_SDMMC1 && !defined(__DOXYGEN__)

 extern SDCDriver SDCD1;

 #endif

 

+#if STM32_SDC_USE_SDMMC2 && !defined(__DOXYGEN__)

+extern SDCDriver SDCD2;

+#endif

+

 #ifdef __cplusplus

 extern "C" {

 #endif