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authorGiovanni Di Sirio <gdisirio@gmail.com>2015-07-29 10:25:34 +0000
committerGiovanni Di Sirio <gdisirio@gmail.com>2015-07-29 10:25:34 +0000
commitade92163ac1dc1fe5c8930495c5e591696a349b9 (patch)
tree14fff97aa307bdc994f9b50badc268e0104aae84 /os/hal/ports/STM32/LLD/DMAv1
parent5e5cb6651a739e36bcbd9bb07dd7aa537af9dbf0 (diff)
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Fixed new DMA driver.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8127 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/LLD/DMAv1')
-rw-r--r--os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c24
1 files changed, 14 insertions, 10 deletions
diff --git a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c
index 74db011d1..6a02152e4 100644
--- a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c
+++ b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c
@@ -101,10 +101,10 @@
#define DMA1_CH7_CMASK 0x00000078U
#endif
#define DMA2_CH1_CMASK 0x00000080U
-#define DMA3_CH2_CMASK 0x00000100U
-#define DMA3_CH3_CMASK 0x00000200U
-#define DMA4_CH4_CMASK 0x00000400U
-#define DMA5_CH5_CMASK 0x00000800U
+#define DMA2_CH2_CMASK 0x00000100U
+#define DMA2_CH3_CMASK 0x00000200U
+#define DMA2_CH4_CMASK 0x00000400U
+#define DMA2_CH5_CMASK 0x00000800U
/*===========================================================================*/
/* Driver exported variables. */
@@ -538,11 +538,13 @@ bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
dma_isr_redir[dmastp->selfindex].dma_param = param;
/* Enabling DMA clocks required by the current streams set.*/
- if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0U)
+ if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) {
rccEnableDMA1(false);
+ }
#if STM32_DMA2_NUM_CHANNELS > 0
- if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0U)
+ if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0U) {
rccEnableDMA2(false);
+ }
#endif
/* Putting the stream in a safe state.*/
@@ -551,7 +553,7 @@ bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
/* Enables the associated IRQ vector if not alread enabled and if a
callback is defined.*/
- if (((dma_streams_mask & dmastp->cmask) != 0U) &&
+ if (((dma_streams_mask & dmastp->cmask) == 0U) &&
(func != NULL)) {
nvicEnableVector(dmastp->vector, priority);
}
@@ -584,7 +586,7 @@ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
"not allocated");
/* Marks the stream as not allocated.*/
- dma_streams_mask &= ~(1 << dmastp->selfindex);
+ dma_streams_mask &= ~(1U << dmastp->selfindex);
/* Disables the associated IRQ vector if it is no more in use.*/
if ((dma_streams_mask & dmastp->cmask) == 0U) {
@@ -596,11 +598,13 @@ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
dma_isr_redir[dmastp->selfindex].dma_param = NULL;
/* Shutting down clocks that are no more required, if any.*/
- if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0U)
+ if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) {
rccDisableDMA1(false);
+ }
#if STM32_DMA2_NUM_CHANNELS > 0
- if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0U)
+ if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0U) {
rccDisableDMA2(false);
+ }
#endif
}