DMAv1 fixes.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8395 35acf78f-673a-0410-8e92-d51de3d6d3f4

1 files changed, 28 insertions, 28 deletions

diff --git a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c
index 97f93340d..2376ab18c 100644
--- a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c
+++ b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c
@@ -139,25 +139,25 @@
  *          instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.

  */

 const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {

-  {DMA1_Channel1, DMA1_CH1_CMASK, &DMA1->IFCR, ADDR_DMA1_CSELR,  0,  0, STM32_DMA1_CH1_NUMBER},

-  {DMA1_Channel2, DMA1_CH2_CMASK, &DMA1->IFCR, ADDR_DMA1_CSELR,  4,  1, STM32_DMA1_CH2_NUMBER},

-  {DMA1_Channel3, DMA1_CH3_CMASK, &DMA1->IFCR, ADDR_DMA1_CSELR,  8,  2, STM32_DMA1_CH3_NUMBER},

-  {DMA1_Channel4, DMA1_CH4_CMASK, &DMA1->IFCR, ADDR_DMA1_CSELR, 12,  3, STM32_DMA1_CH4_NUMBER},

-  {DMA1_Channel5, DMA1_CH5_CMASK, &DMA1->IFCR, ADDR_DMA1_CSELR, 16,  4, STM32_DMA1_CH5_NUMBER},

+  {DMA1, DMA1_Channel1, DMA1_CH1_CMASK, ADDR_DMA1_CSELR,  0,  0, STM32_DMA1_CH1_NUMBER},

+  {DMA1, DMA1_Channel2, DMA1_CH2_CMASK, ADDR_DMA1_CSELR,  4,  1, STM32_DMA1_CH2_NUMBER},

+  {DMA1, DMA1_Channel3, DMA1_CH3_CMASK, ADDR_DMA1_CSELR,  8,  2, STM32_DMA1_CH3_NUMBER},

+  {DMA1, DMA1_Channel4, DMA1_CH4_CMASK, ADDR_DMA1_CSELR, 12,  3, STM32_DMA1_CH4_NUMBER},

+  {DMA1, DMA1_Channel5, DMA1_CH5_CMASK, ADDR_DMA1_CSELR, 16,  4, STM32_DMA1_CH5_NUMBER},

 #if STM32_DMA1_NUM_CHANNELS > 5

-  {DMA1_Channel6, DMA1_CH6_CMASK, &DMA1->IFCR, ADDR_DMA1_CSELR, 20,  5, STM32_DMA1_CH6_NUMBER},

+  {DMA1, DMA1_Channel6, DMA1_CH6_CMASK, ADDR_DMA1_CSELR, 20,  5, STM32_DMA1_CH6_NUMBER},

 #if STM32_DMA1_NUM_CHANNELS > 6

-  {DMA1_Channel7, DMA1_CH7_CMASK, &DMA1->IFCR, ADDR_DMA1_CSELR, 24,  6, STM32_DMA1_CH7_NUMBER},

+  {DMA1, DMA1_Channel7, DMA1_CH7_CMASK, ADDR_DMA1_CSELR, 24,  6, STM32_DMA1_CH7_NUMBER},

 #if STM32_DMA2_NUM_CHANNELS > 0

-  {DMA2_Channel1, DMA2_CH1_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR,  0,  7, STM32_DMA2_CH1_NUMBER},

-  {DMA2_Channel2, DMA2_CH2_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR,  4,  8, STM32_DMA2_CH2_NUMBER},

-  {DMA2_Channel3, DMA2_CH3_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR,  8,  9, STM32_DMA2_CH3_NUMBER},

-  {DMA2_Channel4, DMA2_CH4_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 12, 10, STM32_DMA2_CH4_NUMBER},

-  {DMA2_Channel5, DMA2_CH5_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 16, 11, STM32_DMA2_CH5_NUMBER},

+  {DMA2, DMA2_Channel1, DMA2_CH1_CMASK, ADDR_DMA2_CSELR,  0,  7, STM32_DMA2_CH1_NUMBER},

+  {DMA2, DMA2_Channel2, DMA2_CH2_CMASK, ADDR_DMA2_CSELR,  4,  8, STM32_DMA2_CH2_NUMBER},

+  {DMA2, DMA2_Channel3, DMA2_CH3_CMASK, ADDR_DMA2_CSELR,  8,  9, STM32_DMA2_CH3_NUMBER},

+  {DMA2, DMA2_Channel4, DMA2_CH4_CMASK, ADDR_DMA2_CSELR, 12, 10, STM32_DMA2_CH4_NUMBER},

+  {DMA2, DMA2_Channel5, DMA2_CH5_CMASK, ADDR_DMA2_CSELR, 16, 11, STM32_DMA2_CH5_NUMBER},

 #if STM32_DMA2_NUM_CHANNELS > 5

-  {DMA2_Channel6, DMA2_CH6_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 20, 12, STM32_DMA2_CH6_NUMBER},

+  {DMA2, DMA2_Channel6, DMA2_CH6_CMASK, ADDR_DMA2_CSELR, 20, 12, STM32_DMA2_CH6_NUMBER},

 #if STM32_DMA2_NUM_CHANNELS > 6

-  {DMA2_Channel6, DMA2_CH7_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 24, 13, STM32_DMA2_CH7_NUMBER},

+  {DMA2, DMA2_Channel6, DMA2_CH7_CMASK, ADDR_DMA2_CSELR, 24, 13, STM32_DMA2_CH7_NUMBER},

 #endif

 #endif

 #endif

@@ -197,7 +197,7 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH1_HANDLER) {
 

   OSAL_IRQ_PROLOGUE();

 

-  dmaServeInterrupt(DMA1, 1);

+  dmaServeInterrupt(STM32_DMA1_STREAM1);

 

   OSAL_IRQ_EPILOGUE();

 }

@@ -213,7 +213,7 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH2_HANDLER) {
 

   OSAL_IRQ_PROLOGUE();

 

-  dmaServeInterrupt(DMA1, 2);

+  dmaServeInterrupt(STM32_DMA1_STREAM2);

 

   OSAL_IRQ_EPILOGUE();

 }

@@ -229,7 +229,7 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH3_HANDLER) {
 

   OSAL_IRQ_PROLOGUE();

 

-  dmaServeInterrupt(DMA1, 3);

+  dmaServeInterrupt(STM32_DMA1_STREAM3);

 

   OSAL_IRQ_EPILOGUE();

 }

@@ -245,7 +245,7 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH4_HANDLER) {
 

   OSAL_IRQ_PROLOGUE();

 

-  dmaServeInterrupt(DMA1, 4);

+  dmaServeInterrupt(STM32_DMA1_STREAM4);

 

   OSAL_IRQ_EPILOGUE();

 }

@@ -261,7 +261,7 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH5_HANDLER) {
 

   OSAL_IRQ_PROLOGUE();

 

-  dmaServeInterrupt(DMA1, 5);

+  dmaServeInterrupt(STM32_DMA1_STREAM5);

 

   OSAL_IRQ_EPILOGUE();

 }

@@ -277,7 +277,7 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH6_HANDLER) {
 

   OSAL_IRQ_PROLOGUE();

 

-  dmaServeInterrupt(DMA1, 6);

+  dmaServeInterrupt(STM32_DMA1_STREAM6);

 

   OSAL_IRQ_EPILOGUE();

 }

@@ -293,7 +293,7 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH7_HANDLER) {
 

   OSAL_IRQ_PROLOGUE();

 

-  dmaServeInterrupt(DMA1, 7);

+  dmaServeInterrupt(STM32_DMA1_STREAM7);

 

   OSAL_IRQ_EPILOGUE();

 }

@@ -309,7 +309,7 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH1_HANDLER) {
 

   OSAL_IRQ_PROLOGUE();

 

-  dmaServeInterrupt(DMA2, 1);

+  dmaServeInterrupt(STM32_DMA2_STREAM1);

 

   OSAL_IRQ_EPILOGUE();

 }

@@ -325,7 +325,7 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH2_HANDLER) {
 

   OSAL_IRQ_PROLOGUE();

 

-  dmaServeInterrupt(DMA2, 2);

+  dmaServeInterrupt(STM32_DMA2_STREAM2);

 

   OSAL_IRQ_EPILOGUE();

 }

@@ -341,7 +341,7 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH3_HANDLER) {
 

   OSAL_IRQ_PROLOGUE();

 

-  dmaServeInterrupt(DMA2, 3);

+  dmaServeInterrupt(STM32_DMA2_STREAM3);

 

   OSAL_IRQ_EPILOGUE();

 }

@@ -357,7 +357,7 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH4_HANDLER) {
 

   OSAL_IRQ_PROLOGUE();

 

-  dmaServeInterrupt(DMA2, 4);

+  dmaServeInterrupt(STM32_DMA2_STREAM4);

 

   OSAL_IRQ_EPILOGUE();

 }

@@ -373,7 +373,7 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH5_HANDLER) {
 

   OSAL_IRQ_PROLOGUE();

 

-  dmaServeInterrupt(DMA2, 5);

+  dmaServeInterrupt(STM32_DMA2_STREAM5);

 

   OSAL_IRQ_EPILOGUE();

 }

@@ -389,7 +389,7 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH6_HANDLER) {
 

   OSAL_IRQ_PROLOGUE();

 

-  dmaServeInterrupt(DMA2, 6);

+  dmaServeInterrupt(STM32_DMA2_STREAM6);

 

   OSAL_IRQ_EPILOGUE();

 }

@@ -405,7 +405,7 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH7_HANDLER) {
 

   OSAL_IRQ_PROLOGUE();

 

-  dmaServeInterrupt(DMA2, 7);

+  dmaServeInterrupt(STM32_DMA2_STREAM7);

 

   OSAL_IRQ_EPILOGUE();

 }