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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-09-22 10:19:58 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-09-22 10:19:58 +0000 |
| commit | 4dc2ac9a144af39e4c37515953661f574ec1a5f7 (patch) | |
| tree | 7043d9fa00850b70aea21b53fb70fb7bb0e1c6a2 /os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c | |
| parent | 6a008186f92365a189530329c55d3a127fefebfa (diff) | |
| download | ChibiOS-4dc2ac9a144af39e4c37515953661f574ec1a5f7.tar.gz ChibiOS-4dc2ac9a144af39e4c37515953661f574ec1a5f7.tar.bz2 ChibiOS-4dc2ac9a144af39e4c37515953661f574ec1a5f7.zip | |
Fixed DMAv1 errors.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8323 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c')
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c index 42b0001ce..c4a3c8cd2 100644 --- a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c +++ b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c @@ -135,16 +135,16 @@ const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { {DMA1_Channel5, DMA1_CH5_CMASK, &DMA1->IFCR, ADDR_DMA1_CSELR, 16, 4, STM32_DMA1_CH5_NUMBER},
#if STM32_DMA1_NUM_CHANNELS > 5
{DMA1_Channel6, DMA1_CH6_CMASK, &DMA1->IFCR, ADDR_DMA1_CSELR, 20, 5, STM32_DMA1_CH6_NUMBER},
-#endif
#if STM32_DMA1_NUM_CHANNELS > 6
{DMA1_Channel7, DMA1_CH7_CMASK, &DMA1->IFCR, ADDR_DMA1_CSELR, 24, 6, STM32_DMA1_CH7_NUMBER},
-#endif
#if STM32_DMA2_NUM_CHANNELS > 0
- {DMA2_Channel1, DMA2_CH1_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 0, 8, STM32_DMA2_CH1_NUMBER},
- {DMA2_Channel2, DMA2_CH2_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 4, 9, STM32_DMA2_CH2_NUMBER},
- {DMA2_Channel3, DMA2_CH3_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 8, 10, STM32_DMA2_CH3_NUMBER},
- {DMA2_Channel4, DMA2_CH4_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 12, 11, STM32_DMA2_CH4_NUMBER},
- {DMA2_Channel5, DMA2_CH5_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 16, 13, STM32_DMA2_CH5_NUMBER},
+ {DMA2_Channel1, DMA2_CH1_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 0, 7, STM32_DMA2_CH1_NUMBER},
+ {DMA2_Channel2, DMA2_CH2_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 4, 8, STM32_DMA2_CH2_NUMBER},
+ {DMA2_Channel3, DMA2_CH3_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 8, 9, STM32_DMA2_CH3_NUMBER},
+ {DMA2_Channel4, DMA2_CH4_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 12, 10, STM32_DMA2_CH4_NUMBER},
+ {DMA2_Channel5, DMA2_CH5_CMASK, &DMA2->IFCR, ADDR_DMA2_CSELR, 16, 11, STM32_DMA2_CH5_NUMBER},
+#endif
+#endif
#endif
};
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