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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-07-28 15:04:01 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-07-28 15:04:01 +0000 |
| commit | 4a4cf02fd5fe41339922f59b62ca95491d4178b2 (patch) | |
| tree | 1e384c6ccb859b28c0ec01fedfbd76ce6121e578 /os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c | |
| parent | 2c1d7f6346fe674535f3b57435e44eb4dc680ab9 (diff) | |
| download | ChibiOS-4a4cf02fd5fe41339922f59b62ca95491d4178b2.tar.gz ChibiOS-4a4cf02fd5fe41339922f59b62ca95491d4178b2.tar.bz2 ChibiOS-4a4cf02fd5fe41339922f59b62ca95491d4178b2.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8123 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c')
| -rw-r--r-- | os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c index 4f0d29eb1..57a325c61 100644 --- a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c +++ b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c @@ -42,12 +42,13 @@ /**
* @brief Mask of the DMA1 streams in @p dma_streams_mask.
*/
-#define STM32_DMA1_STREAMS_MASK 0x0000007FU
+#define STM32_DMA1_STREAMS_MASK ((1U << STM32_DMA1_NUM_CHANNELS) - 1U)
/**
* @brief Mask of the DMA2 streams in @p dma_streams_mask.
*/
-#define STM32_DMA2_STREAMS_MASK 0x00000F80U
+#define STM32_DMA2_STREAMS_MASK (((1U << STM32_DMA2_NUM_CHANNELS) - \
+ 1U) << STM32_DMA1_NUM_CHANNELS)
/**
* @brief Post-reset value of the stream CCR register.
@@ -96,13 +97,9 @@ const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = { {DMA1_Channel5, &DMA1->IFCR, ADDR_DMA1_CSELR, 16, 4, STM32_DMA1_CH5_NUMBER},
#if STM32_DMA1_NUM_CHANNELS > 5
{DMA1_Channel6, &DMA1->IFCR, ADDR_DMA1_CSELR, 20, 5, STM32_DMA1_CH6_NUMBER},
-#else
- {NULL, NULL, NULL, 0, 5, 0},
#endif
#if STM32_DMA1_NUM_CHANNELS > 6
{DMA1_Channel7, &DMA1->IFCR, ADDR_DMA1_CSELR, 24, 6, STM32_DMA1_CH7_NUMBER},
-#else
- {NULL, NULL, NULL, 0, 6, 0},
#endif
#if STM32_DMA2_NUM_CHANNELS > 0
{DMA2_Channel1, &DMA2->IFCR, ADDR_DMA2_CSELR, 0, 8, STM32_DMA2_CH1_NUMBER},
|