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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-05-03 13:06:37 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-05-03 13:06:37 +0000 |
| commit | f713242debeb447884d17657c0e26751dc1d84e8 (patch) | |
| tree | b44d4ecd4f0dca687e2ef8eb809580cc1426a8ac /os/hal/ports/STM32/LLD/DACv1/dac_lld.c | |
| parent | f180c606d8485911240ba5441cbd1ca5a9a5d56a (diff) | |
| download | ChibiOS-f713242debeb447884d17657c0e26751dc1d84e8.tar.gz ChibiOS-f713242debeb447884d17657c0e26751dc1d84e8.tar.bz2 ChibiOS-f713242debeb447884d17657c0e26751dc1d84e8.zip | |
Renamed some DAC identifiers for consistency.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7947 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/LLD/DACv1/dac_lld.c')
| -rw-r--r-- | os/hal/ports/STM32/LLD/DACv1/dac_lld.c | 38 |
1 files changed, 22 insertions, 16 deletions
diff --git a/os/hal/ports/STM32/LLD/DACv1/dac_lld.c b/os/hal/ports/STM32/LLD/DACv1/dac_lld.c index f3191e47b..9ba9ef31c 100644 --- a/os/hal/ports/STM32/LLD/DACv1/dac_lld.c +++ b/os/hal/ports/STM32/LLD/DACv1/dac_lld.c @@ -36,19 +36,19 @@ #endif
#define DAC1_CH1_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_DAC1_CH1_DMA_STREAM, \
+ STM32_DMA_GETCHANNEL(STM32_DAC_DAC1_CH1_DMA_STREAM, \
STM32_DAC1_CH1_DMA_CHN)
#define DAC1_CH2_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_DAC1_CH2_DMA_STREAM, \
+ STM32_DMA_GETCHANNEL(STM32_DAC_DAC1_CH2_DMA_STREAM, \
STM32_DAC1_CH2_DMA_CHN)
#define DAC2_CH1_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_DAC2_CH1_DMA_STREAM, \
+ STM32_DMA_GETCHANNEL(STM32_DAC_DAC2_CH1_DMA_STREAM, \
STM32_DAC2_CH1_DMA_CHN)
#define DAC2_CH2_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_DAC2_CH2_DMA_STREAM, \
+ STM32_DMA_GETCHANNEL(STM32_DAC_DAC2_CH2_DMA_STREAM, \
STM32_DAC2_CH2_DMA_CHN)
#define CHANNEL_DATA_OFFSET 12U
@@ -87,13 +87,13 @@ static const dacparams_t dma1_ch1_params = { dataoffset: 0U,
regshift: 0U,
regmask: 0xFFFF0000U,
- dma: STM32_DMA_STREAM(STM32_DAC1_CH1_DMA_STREAM),
+ dma: STM32_DMA_STREAM(STM32_DAC_DAC1_CH1_DMA_STREAM),
dmamode: STM32_DMA_CR_CHSEL(DAC1_CH1_DMA_CHANNEL) |
- STM32_DMA_CR_PL(STM32_DAC1_CH1_DMA_PRIORITY) |
+ STM32_DMA_CR_PL(STM32_DAC_DAC1_CH1_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE,
- dmairqprio: STM32_DAC1_CH1_IRQ_PRIORITY
+ dmairqprio: STM32_DAC_DAC1_CH1_IRQ_PRIORITY
};
#endif
@@ -103,13 +103,13 @@ static const dacparams_t dma1_ch2_params = { dataoffset: CHANNEL_DATA_OFFSET,
regshift: 16U,
regmask: 0x0000FFFFU,
- dma: STM32_DMA_STREAM(STM32_DAC1_CH2_DMA_STREAM),
+ dma: STM32_DMA_STREAM(STM32_DAC_DAC1_CH2_DMA_STREAM),
dmamode: STM32_DMA_CR_CHSEL(DAC1_CH2_DMA_CHANNEL) |
- STM32_DMA_CR_PL(STM32_DAC1_CH2_DMA_PRIORITY) |
+ STM32_DMA_CR_PL(STM32_DAC_DAC1_CH2_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE,
- dmairqprio: STM32_DAC1_CH2_IRQ_PRIORITY
+ dmairqprio: STM32_DAC_DAC1_CH2_IRQ_PRIORITY
};
#endif
@@ -119,13 +119,13 @@ static const dacparams_t dma2_ch1_params = { dataoffset: 0U,
regshift: 0U,
regmask: 0xFFFF0000U,
- dma: STM32_DMA_STREAM(STM32_DAC2_CH1_DMA_STREAM),
+ dma: STM32_DMA_STREAM(STM32_DAC_DAC2_CH1_DMA_STREAM),
dmamode: STM32_DMA_CR_CHSEL(DAC2_CH1_DMA_CHANNEL) |
- STM32_DMA_CR_PL(STM32_DAC2_CH1_DMA_PRIORITY) |
+ STM32_DMA_CR_PL(STM32_DAC_DAC2_CH1_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE,
- dmairqprio: STM32_DAC2_CH1_IRQ_PRIORITY
+ dmairqprio: STM32_DAC_DAC2_CH1_IRQ_PRIORITY
};
#endif
@@ -135,13 +135,13 @@ static const dacparams_t dma1_ch2_params = { dataoffset: CHANNEL_DATA_OFFSET,
regshift: 16U,
regmask: 0x0000FFFFU,
- dma: STM32_DMA_STREAM(STM32_DAC2_CH2_DMA_STREAM),
+ dma: STM32_DMA_STREAM(STM32_DAC_DAC2_CH2_DMA_STREAM),
dmamode: STM32_DMA_CR_CHSEL(DAC2_CH2_DMA_CHANNEL) |
- STM32_DMA_CR_PL(STM32_DAC2_CH2_DMA_PRIORITY) |
+ STM32_DMA_CR_PL(STM32_DAC_DAC2_CH2_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
STM32_DMA_CR_TCIE,
- dmairqprio: STM32_DAC2_CH2_IRQ_PRIORITY
+ dmairqprio: STM32_DAC_DAC2_CH2_IRQ_PRIORITY
};
#endif
@@ -315,7 +315,9 @@ void dac_lld_put_channel(DACDriver *dacp, switch (dacp->config->datamode) {
case DAC_DHRM_12BIT_RIGHT:
+#if STM32_DAC_DUAL_MODE
case DAC_DHRM_12BIT_RIGHT_DUAL:
+#endif
if (channel == 0U) {
dacp->params->dac->DHR12R1 = (uint32_t)sample;
}
@@ -324,7 +326,9 @@ void dac_lld_put_channel(DACDriver *dacp, }
break;
case DAC_DHRM_12BIT_LEFT:
+#if STM32_DAC_DUAL_MODE
case DAC_DHRM_12BIT_LEFT_DUAL:
+#endif
if (channel == 0U) {
dacp->params->dac->DHR12L1 = (uint32_t)sample;
}
@@ -333,7 +337,9 @@ void dac_lld_put_channel(DACDriver *dacp, }
break;
case DAC_DHRM_8BIT_RIGHT:
+#if STM32_DAC_DUAL_MODE
case DAC_DHRM_8BIT_RIGHT_DUAL:
+#endif
if (channel == 0U) {
dacp->params->dac->DHR8R1 = (uint32_t)sample;
}
|