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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-01-17 14:55:12 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-01-17 14:55:12 +0000 |
| commit | c953aa5ac86e4f913c41333a773a0903e0860d35 (patch) | |
| tree | d2c00d4f0eaf25892e5d4f4ade85b2866e2c38de /os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c | |
| parent | df330879bb5c5630e847e2e9eec471080b0d18a4 (diff) | |
| download | ChibiOS-c953aa5ac86e4f913c41333a773a0903e0860d35.tar.gz ChibiOS-c953aa5ac86e4f913c41333a773a0903e0860d35.tar.bz2 ChibiOS-c953aa5ac86e4f913c41333a773a0903e0860d35.zip | |
Defaulted all STM32 drivers to enable peripheral clocks during stop/sleep modes. Now RCC macros are able to set or clear the LP bit of a peripheral.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11300 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c')
| -rw-r--r-- | os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c index f6a2748b3..d16659ddb 100644 --- a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c +++ b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c @@ -535,21 +535,21 @@ void adc_lld_init(void) { #if defined(STM32F3XX)
#if STM32_HAS_ADC1 && STM32_HAS_ADC2
#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2
- rccEnableADC12(false);
+ rccEnableADC12(true);
rccResetADC12();
ADC1_2_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
rccDisableADC12();
#endif
#else
#if STM32_ADC_USE_ADC1
- rccEnableADC12(false);
+ rccEnableADC12(true);
rccResetADC12();
ADC1_COMMON->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
rccDisableADC12();
#endif
#endif
#if STM32_ADC_USE_ADC3 || STM32_ADC_USE_ADC4
- rccEnableADC34(false);
+ rccEnableADC34(true);
rccResetADC34();
ADC3_4_COMMON->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;
rccDisableADC34();
@@ -557,7 +557,7 @@ void adc_lld_init(void) { #endif
#if defined(STM32L4XX)
- rccEnableADC123(false);
+ rccEnableADC123(true);
rccResetADC123();
#if defined(ADC1_2_COMMON)
@@ -599,10 +599,10 @@ void adc_lld_start(ADCDriver *adcp) { clkmask |= (1 << 0);
#if defined(STM32F3XX)
- rccEnableADC12(false);
+ rccEnableADC12(true);
#endif
#if defined(STM32L4XX)
- rccEnableADC123(false);
+ rccEnableADC123(true);
#endif
}
#endif /* STM32_ADC_USE_ADC1 */
@@ -618,10 +618,10 @@ void adc_lld_start(ADCDriver *adcp) { clkmask |= (1 << 1);
#if defined(STM32F3XX)
- rccEnableADC12(false);
+ rccEnableADC12(true);
#endif
#if defined(STM32L4XX)
- rccEnableADC123(false);
+ rccEnableADC123(true);
#endif
}
#endif /* STM32_ADC_USE_ADC2 */
@@ -637,10 +637,10 @@ void adc_lld_start(ADCDriver *adcp) { clkmask |= (1 << 2);
#if defined(STM32F3XX)
- rccEnableADC34(false);
+ rccEnableADC34(true);
#endif
#if defined(STM32L4XX)
- rccEnableADC123(false);
+ rccEnableADC123(true);
#endif
}
#endif /* STM32_ADC_USE_ADC3 */
@@ -656,10 +656,10 @@ void adc_lld_start(ADCDriver *adcp) { clkmask |= (1 << 3);
#if defined(STM32F3XX)
- rccEnableADC34(false);
+ rccEnableADC34(true);
#endif
#if defined(STM32L4XX)
- rccEnableADC123(false);
+ rccEnableADC123(true);
#endif
}
#endif /* STM32_ADC_USE_ADC4 */
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