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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-01-17 14:55:12 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-01-17 14:55:12 +0000 |
| commit | c953aa5ac86e4f913c41333a773a0903e0860d35 (patch) | |
| tree | d2c00d4f0eaf25892e5d4f4ade85b2866e2c38de /os/hal/ports/STM32/LLD/ADCv1 | |
| parent | df330879bb5c5630e847e2e9eec471080b0d18a4 (diff) | |
| download | ChibiOS-c953aa5ac86e4f913c41333a773a0903e0860d35.tar.gz ChibiOS-c953aa5ac86e4f913c41333a773a0903e0860d35.tar.bz2 ChibiOS-c953aa5ac86e4f913c41333a773a0903e0860d35.zip | |
Defaulted all STM32 drivers to enable peripheral clocks during stop/sleep modes. Now RCC macros are able to set or clear the LP bit of a peripheral.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11300 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/LLD/ADCv1')
| -rw-r--r-- | os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.c b/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.c index a7a6c63ee..97412d680 100644 --- a/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.c +++ b/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.c @@ -153,7 +153,7 @@ void adc_lld_init(void) { #endif
/* Calibration procedure.*/
- rccEnableADC1(false);
+ rccEnableADC1(true);
/* CCR setup.*/
#if STM32_ADC_SUPPORTS_PRESCALER
@@ -190,7 +190,7 @@ void adc_lld_start(ADCDriver *adcp) { (void *)adcp);
osalDbgAssert(!b, "stream already allocated");
dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
- rccEnableADC1(false);
+ rccEnableADC1(true);
/* Clock settings.*/
adcp->adc->CFGR2 = STM32_ADC_ADC1_CKMODE;
|