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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-12-09 13:03:19 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-12-09 13:03:19 +0000 |
| commit | 26ed8c9062f0a549507938ec525460f8c10b8acc (patch) | |
| tree | 52b888ed7166bcefa4549714178f85b40a4903e4 /os/hal/ports/STM32/LLD/ADCv1 | |
| parent | 964ca6029035706e5ba5be7a8304eba67920386d (diff) | |
| download | ChibiOS-26ed8c9062f0a549507938ec525460f8c10b8acc.tar.gz ChibiOS-26ed8c9062f0a549507938ec525460f8c10b8acc.tar.bz2 ChibiOS-26ed8c9062f0a549507938ec525460f8c10b8acc.zip | |
ADC reworked.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12467 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os/hal/ports/STM32/LLD/ADCv1')
| -rw-r--r-- | os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.h | 190 |
1 files changed, 53 insertions, 137 deletions
diff --git a/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.h b/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.h index 2da8b80d8..ec33dd626 100644 --- a/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.h +++ b/os/hal/ports/STM32/LLD/ADCv1/hal_adc_lld.h @@ -255,154 +255,70 @@ typedef enum { ADC_ERR_AWD = 2 /**< Analog watchdog triggered. */
} adcerror_t;
-/**
- * @brief Type of a structure representing an ADC driver.
- */
-typedef struct ADCDriver ADCDriver;
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
/**
- * @brief ADC notification callback type.
- *
- * @param[in] adcp pointer to the @p ADCDriver object triggering the
- * callback
- * @param[in] buffer pointer to the most recent samples data
- * @param[in] n number of buffer rows available starting from @p buffer
+ * @brief Low level fields of the ADC driver structure.
*/
-typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
+#define adc_lld_driver_fields \
+ /* Pointer to the ADCx registers block.*/ \
+ ADC_TypeDef *adc; \
+ /* Pointer to associated DMA channel.*/ \
+ const stm32_dma_stream_t *dmastp; \
+ /* DMA mode bit mask.*/ \
+ uint32_t dmamode
/**
- * @brief ADC error callback type.
- *
- * @param[in] adcp pointer to the @p ADCDriver object triggering the
- * callback
- * @param[in] err ADC error code
+ * @brief Low level fields of the ADC configuration structure.
*/
-typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
+#define adc_lld_config_fields \
+ /* Dummy configuration, it is not needed.*/ \
+ uint32_t dummy
/**
- * @brief Conversion group configuration structure.
- * @details This implementation-dependent structure describes a conversion
- * operation.
- * @note The use of this configuration structure requires knowledge of
- * STM32 ADC cell registers interface, please refer to the STM32
- * reference manual for details.
+ * @brief Low level fields of the ADC configuration structure.
*/
-typedef struct {
- /**
- * @brief Enables the circular buffer mode for the group.
- */
- bool circular;
- /**
- * @brief Number of the analog channels belonging to the conversion group.
- */
- adc_channels_num_t num_channels;
- /**
- * @brief Callback function associated to the group or @p NULL.
- */
- adccallback_t end_cb;
- /**
- * @brief Error callback or @p NULL.
- */
- adcerrorcallback_t error_cb;
- /* End of the mandatory fields.*/
- /**
- * @brief ADC CFGR1 register initialization data.
- * @note The bits DMAEN and DMACFG are enforced internally
- * to the driver, keep them to zero.
- * @note The bits @p ADC_CFGR1_CONT or @p ADC_CFGR1_DISCEN must be
- * specified in continuous more or if the buffer depth is
- * greater than one.
- */
- uint32_t cfgr1;
#if (STM32_ADC_SUPPORTS_OVERSAMPLING == TRUE) || defined(__DOXYGEN__)
- /**
- * @brief ADC CFGR2 register initialization data.
- * @note CKMODE bits must not be specified in this field and left to
- * zero.
- */
- uint32_t cfgr2;
-#endif
- /**
- * @brief ADC TR register initialization data.
- */
- uint32_t tr;
- /**
- * @brief ADC SMPR register initialization data.
- */
- uint32_t smpr;
- /**
- * @brief ADC CHSELR register initialization data.
- * @details The number of bits at logic level one in this register must
- * be equal to the number in the @p num_channels field.
- */
- uint32_t chselr;
-} ADCConversionGroup;
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- */
-typedef struct {
- uint32_t dummy;
-} ADCConfig;
-
-/**
- * @brief Structure representing an ADC driver.
- */
-struct ADCDriver {
- /**
- * @brief Driver state.
- */
- adcstate_t state;
- /**
- * @brief Current configuration data.
- */
- const ADCConfig *config;
- /**
- * @brief Current samples buffer pointer or @p NULL.
- */
- adcsample_t *samples;
- /**
- * @brief Current samples buffer depth or @p 0.
- */
- size_t depth;
- /**
- * @brief Current conversion group pointer or @p NULL.
- */
- const ADCConversionGroup *grpp;
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
- /**
- * @brief Waiting thread.
- */
- thread_reference_t thread;
-#endif
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
- /**
- * @brief Mutex protecting the peripheral.
- */
- mutex_t mutex;
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
-#if defined(ADC_DRIVER_EXT_FIELDS)
- ADC_DRIVER_EXT_FIELDS
+#define adc_lld_configuration_group_fields \
+ /* ADC CFGR1 register initialization data. \
+ NOTE: The bits DMAEN and DMACFG are enforced internally \
+ to the driver, keep them to zero. \
+ NOTE: The bits @p ADC_CFGR1_CONT or @p ADC_CFGR1_DISCEN must be \
+ specified in continuous more or if the buffer depth is \
+ greater than one.*/ \
+ uint32_t cfgr1; \
+ /* ADC CFGR2 register initialization data. \
+ NOTE: CKMODE bits must not be specified in this field and left to \
+ zero.*/ \
+ uint32_t cfgr2; \
+ /* ADC TR register initialization data.*/ \
+ uint32_t tr; \
+ /* ADC SMPR register initialization data.*/ \
+ uint32_t smpr; \
+ /* ADC CHSELR register initialization data. \
+ NOTE: The number of bits at logic level one in this register must \
+ be equal to the number in the @p num_channels field.*/ \
+ uint32_t chselr
+#else
+#define adc_lld_configuration_group_fields \
+ /* ADC CFGR1 register initialization data. \
+ NOTE: The bits DMAEN and DMACFG are enforced internally \
+ to the driver, keep them to zero. \
+ NOTE: The bits @p ADC_CFGR1_CONT or @p ADC_CFGR1_DISCEN must be \
+ specified in continuous more or if the buffer depth is \
+ greater than one.*/ \
+ uint32_t cfgr1; \
+ /* ADC TR register initialization data.*/ \
+ uint32_t tr; \
+ /* ADC SMPR register initialization data.*/ \
+ uint32_t smpr; \
+ /* ADC CHSELR register initialization data. \
+ NOTE: The number of bits at logic level one in this register must \
+ be equal to the number in the @p num_channels field.*/ \
+ uint32_t chselr
#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the ADCx registers block.
- */
- ADC_TypeDef *adc;
- /**
- * @brief Pointer to associated DMA channel.
- */
- const stm32_dma_stream_t *dmastp;
- /**
- * @brief DMA mode bit mask.
- */
- uint32_t dmamode;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
/**
* @brief Changes the value of the ADC CCR register.
|