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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-09-22 12:43:39 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-09-22 12:43:39 +0000 |
| commit | e9ffaf9bdc231c69adffd5486c2949f21390e6e1 (patch) | |
| tree | 6e70b0f2705345ca8a6d354dab9364ce07529659 /os/hal/ports/SPC5/SPC560Bxx | |
| parent | c0a616c52b6c00aeee8917329bf8659d3062a7bc (diff) | |
| download | ChibiOS-e9ffaf9bdc231c69adffd5486c2949f21390e6e1.tar.gz ChibiOS-e9ffaf9bdc231c69adffd5486c2949f21390e6e1.tar.bz2 ChibiOS-e9ffaf9bdc231c69adffd5486c2949f21390e6e1.zip | |
Forked SPC5 drivers from SPC5-HAL project, not all of them, just the one needed for supporting the PPC port.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10679 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/SPC5/SPC560Bxx')
| -rw-r--r-- | os/hal/ports/SPC5/SPC560Bxx/cfg/mcuconf.h.ftl | 330 | ||||
| -rw-r--r-- | os/hal/ports/SPC5/SPC560Bxx/hal_lld.c | 279 | ||||
| -rw-r--r-- | os/hal/ports/SPC5/SPC560Bxx/hal_lld.h | 779 | ||||
| -rw-r--r-- | os/hal/ports/SPC5/SPC560Bxx/platform.mk | 22 | ||||
| -rw-r--r-- | os/hal/ports/SPC5/SPC560Bxx/registers.h | 60 | ||||
| -rw-r--r-- | os/hal/ports/SPC5/SPC560Bxx/spc5_registry.h | 676 | ||||
| -rw-r--r-- | os/hal/ports/SPC5/SPC560Bxx/typedefs.h | 38 | ||||
| -rw-r--r-- | os/hal/ports/SPC5/SPC560Bxx/xpc560b.h | 6551 |
8 files changed, 8735 insertions, 0 deletions
diff --git a/os/hal/ports/SPC5/SPC560Bxx/cfg/mcuconf.h.ftl b/os/hal/ports/SPC5/SPC560Bxx/cfg/mcuconf.h.ftl new file mode 100644 index 000000000..9782d053f --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Bxx/cfg/mcuconf.h.ftl @@ -0,0 +1,330 @@ +[#ftl]
+[@pp.dropOutputFile /]
+[@pp.changeOutputFile name="mcuconf.h" /]
+/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+/*
+ * SPC560Bxx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 1...15 Lowest...Highest.
+ * DMA priorities:
+ * 0...15 Highest...Lowest.
+ */
+
+#define SPC560Bxx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define SPC5_NO_INIT ${conf.instance.initialization_settings.do_not_init.value[0]?upper_case}
+#define SPC5_ALLOW_OVERCLOCK ${conf.instance.initialization_settings.allow_overclocking.value[0]?upper_case}
+#define SPC5_DISABLE_WATCHDOG ${conf.instance.initialization_settings.disable_watchdog.value[0]?upper_case}
+#define SPC5_FMPLL0_IDF_VALUE ${conf.instance.initialization_settings.fmpll0_settings.idf_value.value[0]}
+#define SPC5_FMPLL0_NDIV_VALUE ${conf.instance.initialization_settings.fmpll0_settings.ndiv_value.value[0]}
+#define SPC5_FMPLL0_ODF ${conf.instance.initialization_settings.fmpll0_settings.odf_value.value[0]}
+#define SPC5_XOSCDIV_VALUE ${conf.instance.initialization_settings.clocks.fxosc_divider.value[0]}
+#define SPC5_IRCDIV_VALUE ${conf.instance.initialization_settings.clocks.firc_divider.value[0]}
+#define SPC5_PERIPHERAL1_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.peripheral_set_1_clock_divider.value[0]}
+#define SPC5_PERIPHERAL2_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.peripheral_set_2_clock_divider.value[0]}
+#define SPC5_PERIPHERAL3_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.peripheral_set_3_clock_divider.value[0]}
+#define SPC5_CLOCK_FAILURE_HOOK() ${conf.instance.initialization_settings.clocks.clock_failure_hook.value[0]}
+
+#define SPC5_EMIOS0_GPRE_VALUE ${conf.instance.initialization_settings.clocks.emios0_global_prescaler.value[0]?number}
+#define SPC5_EMIOS1_GPRE_VALUE ${conf.instance.initialization_settings.clocks.emios1_global_prescaler.value[0]?number}
+
+/*
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP1PRI(1) | \
+ EDMA_CR_GRP0PRI(0) | \
+ EDMA_CR_EMLM | \
+ EDMA_CR_ERGA)
+#define SPC5_EDMA_GROUP0_PRIORITIES [#rt/]
+[#list conf.instance.edma_settings.group_0_channels_priorities.* as channel]
+ [#if channel_has_next]
+${channel.value[0]}, [#rt/]
+ [#else]
+${channel.value[0]}
+ [/#if]
+[/#list]
+#define SPC5_EDMA_ERROR_IRQ_PRIO 12
+#define SPC5_EDMA_ERROR_HANDLER() osalSysHalt("DMA failure")
+
+/*
+ * SERIAL driver system settings.
+ */
+#define SPC5_SERIAL_USE_LINFLEX0 ${(conf.instance.linflex_settings.linflex0.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX1 ${(conf.instance.linflex_settings.linflex1.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX2 ${(conf.instance.linflex_settings.linflex2.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX3 ${(conf.instance.linflex_settings.linflex3.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX4 ${(conf.instance.linflex_settings.linflex4.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX5 ${(conf.instance.linflex_settings.linflex5.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX6 ${(conf.instance.linflex_settings.linflex6.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX7 ${(conf.instance.linflex_settings.linflex7.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX8 ${(conf.instance.linflex_settings.linflex8.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX9 ${(conf.instance.linflex_settings.linflex9.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_LINFLEX0_PRIORITY ${conf.instance.irq_priority_settings.linflex0.value[0]}
+#define SPC5_SERIAL_LINFLEX1_PRIORITY ${conf.instance.irq_priority_settings.linflex1.value[0]}
+#define SPC5_SERIAL_LINFLEX2_PRIORITY ${conf.instance.irq_priority_settings.linflex2.value[0]}
+#define SPC5_SERIAL_LINFLEX3_PRIORITY ${conf.instance.irq_priority_settings.linflex3.value[0]}
+#define SPC5_SERIAL_LINFLEX4_PRIORITY ${conf.instance.irq_priority_settings.linflex4.value[0]}
+#define SPC5_SERIAL_LINFLEX5_PRIORITY ${conf.instance.irq_priority_settings.linflex5.value[0]}
+#define SPC5_SERIAL_LINFLEX6_PRIORITY ${conf.instance.irq_priority_settings.linflex6.value[0]}
+#define SPC5_SERIAL_LINFLEX7_PRIORITY ${conf.instance.irq_priority_settings.linflex7.value[0]}
+#define SPC5_SERIAL_LINFLEX8_PRIORITY ${conf.instance.irq_priority_settings.linflex8.value[0]}
+#define SPC5_SERIAL_LINFLEX9_PRIORITY ${conf.instance.irq_priority_settings.linflex9.value[0]}
+
+/*
+ * SPI driver system settings.
+ */
+#define SPC5_SPI_USE_DSPI0 ${conf.instance.dspi_settings.dspi_0.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI1 ${conf.instance.dspi_settings.dspi_1.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI2 ${conf.instance.dspi_settings.dspi_2.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI3 ${conf.instance.dspi_settings.dspi_3.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI4 ${conf.instance.dspi_settings.dspi_4.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI5 ${conf.instance.dspi_settings.dspi_5.value[0]?upper_case}
+#define SPC5_SPI_DMA_MODE SPC5_SPI_DMA_${conf.instance.dspi_settings.dma_mode.value[0]?upper_case?replace(" ", "_")}
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs3[0].@index[0]?trim?number] /]
+[#assign s4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs4[0].@index[0]?trim?number] /]
+[#assign s5 = [""," | SPC5_MCR_PCSIS5"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs5[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI0_MCR (0${s0 + s1 + s2 + s3 + s4 + s5})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs3[0].@index[0]?trim?number] /]
+[#assign s4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs4[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI1_MCR (0${s0 + s1 + s2 + s3 + s4})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs3[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI2_MCR (0${s0 + s1 + s2 + s3})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_3___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_3___pcs1[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI3_MCR (0${s0 + s1})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_4___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_4___pcs1[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI4_MCR (0${s0 + s1})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_5___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_5___pcs1[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI5_MCR (0${s0 + s1})
+#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_tx1.value[0]}
+#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_tx2.value[0]}
+#define SPC5_SPI_DSPI0_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_rx.value[0]}
+#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_tx1.value[0]}
+#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_tx2.value[0]}
+#define SPC5_SPI_DSPI1_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_rx.value[0]}
+#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi2_tx1.value[0]}
+#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi2_tx2.value[0]}
+#define SPC5_SPI_DSPI2_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi2_rx.value[0]}
+#define SPC5_SPI_DSPI3_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi3_tx1.value[0]}
+#define SPC5_SPI_DSPI3_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi3_tx2.value[0]}
+#define SPC5_SPI_DSPI3_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi3_rx.value[0]}
+#define SPC5_SPI_DSPI4_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi4_tx1.value[0]}
+#define SPC5_SPI_DSPI4_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi4_tx2.value[0]}
+#define SPC5_SPI_DSPI4_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi4_rx.value[0]}
+#define SPC5_SPI_DSPI5_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi5_tx1.value[0]}
+#define SPC5_SPI_DSPI5_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi5_tx2.value[0]}
+#define SPC5_SPI_DSPI5_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi5_rx.value[0]}
+#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_0.value[0]}
+#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_1.value[0]}
+#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_2.value[0]}
+#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_3.value[0]}
+#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_4.value[0]}
+#define SPC5_SPI_DSPI5_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_5.value[0]}
+#define SPC5_SPI_DSPI0_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_0.value[0]}
+#define SPC5_SPI_DSPI1_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_1.value[0]}
+#define SPC5_SPI_DSPI2_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_2.value[0]}
+#define SPC5_SPI_DSPI3_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_3.value[0]}
+#define SPC5_SPI_DSPI4_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_4.value[0]}
+#define SPC5_SPI_DSPI5_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_5.value[0]}
+#define SPC5_SPI_DMA_ERROR_HOOK(spip) ${conf.instance.dspi_settings.dma_error_hook.value[0]}
+
+/*
+ * ICU-PWM driver system settings.
+ */
+#define SPC5_ICU_USE_EMIOS0_CH0 ${conf.instance.emios_settings.emios0_ch0.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH1 ${conf.instance.emios_settings.emios0_ch1.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH2 ${conf.instance.emios_settings.emios0_ch2.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH3 ${conf.instance.emios_settings.emios0_ch3.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH4 ${conf.instance.emios_settings.emios0_ch4.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH5 ${conf.instance.emios_settings.emios0_ch5.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH6 ${conf.instance.emios_settings.emios0_ch6.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH7 ${conf.instance.emios_settings.emios0_ch7.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH24 ${conf.instance.emios_settings.emios0_ch24.value[0]?upper_case}
+
+#define SPC5_PWM_USE_EMIOS0_GROUP0 ${conf.instance.emios_settings.emios0_group0.value[0]?upper_case}
+#define SPC5_PWM_USE_EMIOS0_GROUP1 ${conf.instance.emios_settings.emios0_group1.value[0]?upper_case}
+
+#define SPC5_EMIOS0_GFR_F0F1_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc0.value[0]}
+#define SPC5_EMIOS0_GFR_F2F3_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc1.value[0]}
+#define SPC5_EMIOS0_GFR_F4F5_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc2.value[0]}
+#define SPC5_EMIOS0_GFR_F6F7_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc3.value[0]}
+#define SPC5_EMIOS0_GFR_F8F9_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc4.value[0]}
+#define SPC5_EMIOS0_GFR_F10F11_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc5.value[0]}
+#define SPC5_EMIOS0_GFR_F12F13_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc6.value[0]}
+#define SPC5_EMIOS0_GFR_F14F15_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc7.value[0]}
+#define SPC5_EMIOS0_GFR_F16F17_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc8.value[0]}
+#define SPC5_EMIOS0_GFR_F18F19_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc9.value[0]}
+#define SPC5_EMIOS0_GFR_F20F21_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc10.value[0]}
+#define SPC5_EMIOS0_GFR_F22F23_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc11.value[0]}
+#define SPC5_EMIOS0_GFR_F24F25_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc12.value[0]}
+
+#define SPC5_EMIOS0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_EMIOS0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_ICU_USE_EMIOS1_CH24 ${conf.instance.emios_settings.emios1_ch24.value[0]?upper_case}
+
+#define SPC5_PWM_USE_EMIOS1_GROUP0 ${conf.instance.emios_settings.emios1_group0.value[0]?upper_case}
+#define SPC5_PWM_USE_EMIOS1_GROUP1 ${conf.instance.emios_settings.emios1_group1.value[0]?upper_case}
+#define SPC5_PWM_USE_EMIOS1_GROUP2 ${conf.instance.emios_settings.emios1_group2.value[0]?upper_case}
+
+#define SPC5_EMIOS1_GFR_F0F1_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc0.value[0]}
+#define SPC5_EMIOS1_GFR_F2F3_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc1.value[0]}
+#define SPC5_EMIOS1_GFR_F4F5_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc2.value[0]}
+#define SPC5_EMIOS1_GFR_F6F7_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc3.value[0]}
+#define SPC5_EMIOS1_GFR_F8F9_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc4.value[0]}
+#define SPC5_EMIOS1_GFR_F10F11_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc5.value[0]}
+#define SPC5_EMIOS1_GFR_F12F13_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc6.value[0]}
+#define SPC5_EMIOS1_GFR_F14F15_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc7.value[0]}
+#define SPC5_EMIOS1_GFR_F16F17_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc8.value[0]}
+#define SPC5_EMIOS1_GFR_F18F19_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc9.value[0]}
+#define SPC5_EMIOS1_GFR_F20F21_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc10.value[0]}
+#define SPC5_EMIOS1_GFR_F22F23_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc11.value[0]}
+#define SPC5_EMIOS1_GFR_F24F25_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc12.value[0]}
+
+#define SPC5_EMIOS1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_EMIOS1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+/*
+ * CAN driver system settings.
+ */
+#define SPC5_CAN_USE_FILTERS ${conf.instance.flexcan_settings.flexcan_enable_filters.value[0]?upper_case}
+
+#define SPC5_CAN_USE_FLEXCAN0 ${conf.instance.flexcan_settings.flexcan0.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN0_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan0_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN0_PRIORITY ${conf.instance.irq_priority_settings.flexcan0.value[0]}
+#define SPC5_CAN_NUM_RX_MAILBOXES ${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_rx_mailboxes.value[0]}
+#define SPC5_CAN_NUM_TX_MAILBOXES ${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_tx_mailboxes.value[0]}
+#define SPC5_CAN_FLEXCAN0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN1 ${conf.instance.flexcan_settings.flexcan1.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN1_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan1_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN1_PRIORITY ${conf.instance.irq_priority_settings.flexcan1.value[0]}
+#define SPC5_CAN_FLEXCAN1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN2 ${conf.instance.flexcan_settings.flexcan2.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN2_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan2_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN2_PRIORITY ${conf.instance.irq_priority_settings.flexcan2.value[0]}
+#define SPC5_CAN_FLEXCAN2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN3 ${conf.instance.flexcan_settings.flexcan3.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN3_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan3_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN3_PRIORITY ${conf.instance.irq_priority_settings.flexcan3.value[0]}
+#define SPC5_CAN_FLEXCAN3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN4 ${conf.instance.flexcan_settings.flexcan4.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN4_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan4_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN4_PRIORITY ${conf.instance.irq_priority_settings.flexcan4.value[0]}
+#define SPC5_CAN_FLEXCAN4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN5 ${conf.instance.flexcan_settings.flexcan5.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN5_PRIORITY ${conf.instance.irq_priority_settings.flexcan5.value[0]}
+#define SPC5_CAN_FLEXCAN5_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan5_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN5_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN5_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+/*
+* ADC driver system settings.
+*/
+[#if conf.instance.adc_settings.adc0_clock_divider.value[0] == "Peripheral clock frequency"]
+ [#assign clk_f0 = "PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[#else]
+ [#assign clk_f0 = "HALF_PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[/#if]
+
+[#if conf.instance.adc_settings.dma_mode.value[0] == "true" ]
+ [#assign dma_mode = "SPC5_ADC_DMA_ON"]
+[#else]
+ [#assign dma_mode = "SPC5_ADC_DMA_OFF"]
+[/#if]
+
+#define SPC5_ADC_DMA_MODE ${dma_mode}
+
+#define SPC5_ADC_USE_ADC0 ${conf.instance.adc_settings.adc0.value[0]?upper_case}
+#define SPC5_ADC_ADC0_CLK_FREQUENCY ${clk_f0}
+#define SPC5_ADC_ADC0_AUTO_CLOCK_OFF ${conf.instance.adc_settings.adc0_auto_clock_off_mode.value[0]?upper_case}
+#define SPC5_ADC_ADC0_WD_PRIORITY ${conf.instance.irq_priority_settings.adc0.value[0]}
+#define SPC5_ADC_ADC0_EOC_PRIORITY SPC5_ADC_ADC0_WD_PRIORITY
+#define SPC5_ADC_ADC0_DMA_CH_ID ${conf.instance.edma_mux_settings.adc_channels.adc0.value[0]}
+#define SPC5_ADC_ADC0_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.adc0.value[0]}
+#define SPC5_ADC_ADC0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_ADC_ADC0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+
+
+[#if conf.instance.adc_settings.adc1_clock_divider.value[0] == "Peripheral clock frequency"]
+ [#assign clk_f1 = "PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[#else]
+ [#assign clk_f1 = "HALF_PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[/#if]
+#define SPC5_ADC_USE_ADC1 ${conf.instance.adc_settings.adc1.value[0]?upper_case}
+#define SPC5_ADC_ADC1_CLK_FREQUENCY ${clk_f1}
+#define SPC5_ADC_ADC1_AUTO_CLOCK_OFF ${conf.instance.adc_settings.adc1_auto_clock_off_mode.value[0]?upper_case}
+#define SPC5_ADC_ADC1_WD_PRIORITY ${conf.instance.irq_priority_settings.adc1.value[0]}
+#define SPC5_ADC_ADC1_EOC_PRIORITY SPC5_ADC_ADC1_WD_PRIORITY
+#define SPC5_ADC_ADC1_DMA_CH_ID ${conf.instance.edma_mux_settings.adc_channels.adc1.value[0]}
+#define SPC5_ADC_ADC1_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.adc1.value[0]}
+#define SPC5_ADC_ADC1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_ADC_ADC1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#endif /* _MCUCONF_H_ */
diff --git a/os/hal/ports/SPC5/SPC560Bxx/hal_lld.c b/os/hal/ports/SPC5/SPC560Bxx/hal_lld.c new file mode 100644 index 000000000..5a9481c6d --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Bxx/hal_lld.c @@ -0,0 +1,279 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560BCxx/hal_lld.c
+ * @brief SPC560B/Cxx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief PIT channel 0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector59) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ osalSysLockFromISR();
+ osalOsTimerHandlerI();
+ osalSysUnlockFromISR();
+
+ /* Resets the PIT channel 0 IRQ flag.*/
+ PIT.CH[0].TFLG.R = 1;
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+ uint32_t reg;
+
+ /* The system is switched to the RUN0 mode, the default for normal
+ operations.*/
+ if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == OSAL_FAILED) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+ /* PIT channel 0 initialization for Kernel ticks, the PIT is configured
+ to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
+ modes.*/
+ INTC.PSR[59].R = SPC5_PIT0_IRQ_PRIORITY;
+ halSPCSetPeripheralClockMode(92,
+ SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
+ reg = halSPCGetSystemClock() / OSAL_ST_FREQUENCY - 1;
+ PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */
+ PIT.CH[0].LDVAL.R = reg;
+ PIT.CH[0].CVAL.R = reg;
+ PIT.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */
+ PIT.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */
+
+ /* EDMA initialization.*/
+ edmaInit();
+}
+
+/**
+ * @brief SPC560B/Cxx clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h and
+ * @p hal_lld.h
+ * @note This function must be invoked only after the system reset.
+ *
+ * @special
+ */
+void spc_clock_init(void) {
+
+ /* Waiting for IRC stabilization before attempting anything else.*/
+ while (!ME.GS.B.RC)
+ ;
+
+#if !SPC5_NO_INIT
+
+#if SPC5_DISABLE_WATCHDOG
+ /* SWT disabled.*/
+ SWT.SR.R = 0xC520;
+ SWT.SR.R = 0xD928;
+ SWT.CR.R = 0xFF00000A;
+#endif
+
+ /* SSCM initialization. Setting up the most restrictive handling of
+ invalid accesses to peripherals.*/
+ SSCM.ERROR.R = 3; /* PAE and RAE bits. */
+
+ /* RGM errors clearing.*/
+ RGM.FES.R = 0xFFFF;
+ RGM.DES.R = 0xFFFF;
+
+ /* Oscillators dividers setup.*/
+ CGM.FIRC_CTL.B.RCDIV = SPC5_IRCDIV_VALUE - 1;
+ CGM.FXOSC_CTL.B.OSCDIV = SPC5_XOSCDIV_VALUE - 1;
+
+ /* The system must be in DRUN mode on entry, if this is not the case then
+ it is considered a serious anomaly.*/
+ if (ME.GS.B.CURRENTMODE != SPC5_RUNMODE_DRUN) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+#if defined(SPC5_OSC_BYPASS)
+ /* If the board is equipped with an oscillator instead of a xtal then the
+ bypass must be activated.*/
+ CGM.FXOSC_CTL.B.OSCBYP = TRUE;
+#endif /* SPC5_OSC_BYPASS */
+
+ /* Setting the various dividers and source selectors.*/
+ CGM.SC_DC[0].R = SPC5_CGM_SC_DC0;
+ CGM.SC_DC[1].R = SPC5_CGM_SC_DC1;
+ CGM.SC_DC[2].R = SPC5_CGM_SC_DC2;
+
+ /* Initialization of the FMPLLs settings.*/
+ CGM.FMPLL_CR.R = SPC5_FMPLL0_ODF |
+ ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
+ (SPC5_FMPLL0_NDIV_VALUE << 16);
+ CGM.FMPLL_MR.R = 0; /* TODO: Add a setting. */
+
+ /* Run modes initialization.*/
+ ME.IS.R = 8; /* Resetting I_ICONF status.*/
+ ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */
+ ME.TEST.R = SPC5_ME_TEST_MC_BITS; /* TEST run mode. */
+ ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */
+ ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */
+ ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */
+ ME.RUN[1].R = SPC5_ME_RUN1_MC_BITS; /* RUN1 run mode. */
+ ME.RUN[2].R = SPC5_ME_RUN2_MC_BITS; /* RUN2 run mode. */
+ ME.RUN[3].R = SPC5_ME_RUN3_MC_BITS; /* RUN0 run mode. */
+ ME.HALT0.R = SPC5_ME_HALT0_MC_BITS; /* HALT0 run mode. */
+ ME.STOP0.R = SPC5_ME_STOP0_MC_BITS; /* STOP0 run mode. */
+ ME.STANDBY0.R = SPC5_ME_STANDBY0_MC_BITS; /* STANDBY0 run mode. */
+ if (ME.IS.B.ICONF) {
+ /* Configuration rejected.*/
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+ /* Peripherals run and low power modes initialization.*/
+ ME.RUNPC[0].R = SPC5_ME_RUN_PC0_BITS;
+ ME.RUNPC[1].R = SPC5_ME_RUN_PC1_BITS;
+ ME.RUNPC[2].R = SPC5_ME_RUN_PC2_BITS;
+ ME.RUNPC[3].R = SPC5_ME_RUN_PC3_BITS;
+ ME.RUNPC[4].R = SPC5_ME_RUN_PC4_BITS;
+ ME.RUNPC[5].R = SPC5_ME_RUN_PC5_BITS;
+ ME.RUNPC[6].R = SPC5_ME_RUN_PC6_BITS;
+ ME.RUNPC[7].R = SPC5_ME_RUN_PC7_BITS;
+ ME.LPPC[0].R = SPC5_ME_LP_PC0_BITS;
+ ME.LPPC[1].R = SPC5_ME_LP_PC1_BITS;
+ ME.LPPC[2].R = SPC5_ME_LP_PC2_BITS;
+ ME.LPPC[3].R = SPC5_ME_LP_PC3_BITS;
+ ME.LPPC[4].R = SPC5_ME_LP_PC4_BITS;
+ ME.LPPC[5].R = SPC5_ME_LP_PC5_BITS;
+ ME.LPPC[6].R = SPC5_ME_LP_PC6_BITS;
+ ME.LPPC[7].R = SPC5_ME_LP_PC7_BITS;
+
+ /* CFLASH settings calculated for a maximum clock of 64MHz.*/
+ CFLASH.PFCR0.B.BK0_APC = 2;
+ CFLASH.PFCR0.B.BK0_RWSC = 2;
+
+ /* CMU clock enable */
+ halSPCSetPeripheralClockMode(104,
+ SPC5_ME_PCTL_RUN(1) | SPC5_ME_PCTL_LP(2));
+
+ /* Switches again to DRUN mode (current mode) in order to update the
+ settings.*/
+ if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == OSAL_FAILED) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+#endif /* !SPC5_NO_INIT */
+}
+
+/**
+ * @brief Switches the system to the specified run mode.
+ *
+ * @param[in] mode one of the possible run modes
+ *
+ * @return The operation status.
+ * @retval OSAL_SUCCESS if the switch operation has been completed.
+ * @retval OSAL_FAILED if the switch operation failed.
+ */
+bool halSPCSetRunMode(spc5_runmode_t mode) {
+
+ /* Clearing status register bits I_IMODE(4) and I_IMTC(1).*/
+ ME.IS.R = 5;
+
+ /* Starts a transition process.*/
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
+
+ /* Waits for the mode switch or an error condition.*/
+ while (TRUE) {
+ uint32_t r = ME.IS.R;
+ if (r & 1)
+ return OSAL_SUCCESS;
+ if (r & 4)
+ return OSAL_FAILED;
+ }
+}
+
+/**
+ * @brief Changes the clock mode of a peripheral.
+ *
+ * @param[in] n index of the @p PCTL register
+ * @param[in] pctl new value for the @p PCTL register
+ *
+ * @notapi
+ */
+void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
+ uint32_t mode;
+
+ ME.PCTL[n].R = pctl;
+ mode = ME.MCTL.B.TARGETMODE;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
+}
+
+#if !SPC5_NO_INIT || defined(__DOXYGEN__)
+/**
+ * @brief Returns the system clock under the current run mode.
+ *
+ * @return The system clock in Hertz.
+ */
+uint32_t halSPCGetSystemClock(void) {
+ uint32_t sysclk;
+
+ sysclk = ME.GS.B.SYSCLK;
+ switch (sysclk) {
+ case SPC5_ME_GS_SYSCLK_IRC:
+ return SPC5_IRC_CLK;
+ case SPC5_ME_GS_SYSCLK_DIVIRC:
+ return SPC5_IRC_CLK / SPC5_IRCDIV_VALUE;
+ case SPC5_ME_GS_SYSCLK_XOSC:
+ return SPC5_XOSC_CLK / SPC5_XOSCDIV_VALUE;
+ case SPC5_ME_GS_SYSCLK_DIVXOSC:
+ return SPC5_XOSC_CLK;
+ case SPC5_ME_GS_SYSCLK_FMPLL0:
+ return SPC5_FMPLL0_CLK;
+ default:
+ return 0;
+ }
+}
+#endif /* !SPC5_NO_INIT */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560Bxx/hal_lld.h b/os/hal/ports/SPC5/SPC560Bxx/hal_lld.h new file mode 100644 index 000000000..0e9e339bd --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Bxx/hal_lld.h @@ -0,0 +1,779 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Bxx/hal_lld.h
+ * @brief SPC560Bxx HAL subsystem low level driver header.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - SPC5_XOSC_CLK.
+ * - SPC5_OSC_BYPASS (optionally).
+ * .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
+
+#include "registers.h"
+#include "spc5_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS FALSE
+
+/**
+ * @name Platform identification
+ * @{
+ */
+#define PLATFORM_NAME "SPC560Bxx Car Body and Convenience"
+/** @} */
+
+/**
+ * @name Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief Maximum XOSC clock frequency.
+ */
+#define SPC5_XOSC_CLK_MAX 16000000
+
+/**
+ * @brief Minimum XOSC clock frequency.
+ */
+#define SPC5_XOSC_CLK_MIN 4000000
+
+/**
+ * @brief Maximum SXOSC clock frequency.
+ */
+#define SPC5_SXOSC_CLK_MAX 40000
+
+/**
+ * @brief Minimum SXOSC clock frequency.
+ */
+#define SPC5_SXOSC_CLK_MIN 32000
+
+/**
+ * @brief Maximum FMPLLs input clock frequency.
+ */
+#define SPC5_FMPLLIN_MIN 4000000
+
+/**
+ * @brief Maximum FMPLLs input clock frequency.
+ */
+#define SPC5_FMPLLIN_MAX 64000000
+
+/**
+ * @brief Maximum FMPLLs VCO clock frequency.
+ */
+#define SPC5_FMPLLVCO_MAX 512000000
+
+/**
+ * @brief Maximum FMPLLs VCO clock frequency.
+ */
+#define SPC5_FMPLLVCO_MIN 256000000
+
+/**
+ * @brief Maximum FMPLL0 output clock frequency.
+ */
+#define SPC5_FMPLL0_CLK_MAX 64000000
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define SPC5_IRC_CLK 16000000 /**< Internal fast RC
+ oscillator. */
+#define SPC5_SIRC_CLK 128000 /**< Internal RC slow
+ oscillator. */
+/** @} */
+
+/**
+ * @name FMPLL_CR register bits definitions
+ * @{
+ */
+#define SPC5_FMPLL_ODF_DIV2 (0U << 24)
+#define SPC5_FMPLL_ODF_DIV4 (1U << 24)
+#define SPC5_FMPLL_ODF_DIV8 (2U << 24)
+#define SPC5_FMPLL_ODF_DIV16 (3U << 24)
+/** @} */
+
+/**
+ * @name ME_GS register bits definitions
+ * @{
+ */
+#define SPC5_ME_GS_SYSCLK_MASK (15U << 0)
+#define SPC5_ME_GS_SYSCLK_IRC (0U << 0)
+#define SPC5_ME_GS_SYSCLK_DIVIRC (1U << 0)
+#define SPC5_ME_GS_SYSCLK_XOSC (2U << 0)
+#define SPC5_ME_GS_SYSCLK_DIVXOSC (3U << 0)
+#define SPC5_ME_GS_SYSCLK_FMPLL0 (4U << 0)
+/** @} */
+
+/**
+ * @name ME_ME register bits definitions
+ * @{
+ */
+#define SPC5_ME_ME_RESET (1U << 0)
+#define SPC5_ME_ME_TEST (1U << 1)
+#define SPC5_ME_ME_SAFE (1U << 2)
+#define SPC5_ME_ME_DRUN (1U << 3)
+#define SPC5_ME_ME_RUN0 (1U << 4)
+#define SPC5_ME_ME_RUN1 (1U << 5)
+#define SPC5_ME_ME_RUN2 (1U << 6)
+#define SPC5_ME_ME_RUN3 (1U << 7)
+#define SPC5_ME_ME_HALT0 (1U << 8)
+#define SPC5_ME_ME_STOP0 (1U << 10)
+#define SPC5_ME_ME_STANDBY0 (1U << 13)
+/** @} */
+
+/**
+ * @name ME_xxx_MC registers bits definitions
+ * @{
+ */
+#define SPC5_ME_MC_SYSCLK_MASK (15U << 0)
+#define SPC5_ME_MC_SYSCLK(n) ((n) << 0)
+#define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0)
+#define SPC5_ME_MC_SYSCLK_DIVIRC SPC5_ME_MC_SYSCLK(1)
+#define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2)
+#define SPC5_ME_MC_SYSCLK_DIVXOSC SPC5_ME_MC_SYSCLK(3)
+#define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4)
+#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15)
+#define SPC5_ME_MC_IRCON (1U << 4)
+#define SPC5_ME_MC_XOSC0ON (1U << 5)
+#define SPC5_ME_MC_PLL0ON (1U << 6)
+#define SPC5_ME_MC_CFLAON_MASK (3U << 16)
+#define SPC5_ME_MC_CFLAON(n) ((n) << 16)
+#define SPC5_ME_MC_CFLAON_PD (1U << 16)
+#define SPC5_ME_MC_CFLAON_LP (2U << 16)
+#define SPC5_ME_MC_CFLAON_NORMAL (3U << 16)
+#define SPC5_ME_MC_DFLAON_MASK (3U << 18)
+#define SPC5_ME_MC_DFLAON(n) ((n) << 18)
+#define SPC5_ME_MC_DFLAON_PD (1U << 18)
+#define SPC5_ME_MC_DFLAON_LP (2U << 18)
+#define SPC5_ME_MC_DFLAON_NORMAL (3U << 18)
+#define SPC5_ME_MC_MVRON (1U << 20)
+#define SPC5_ME_MC_PDO (1U << 23)
+/** @} */
+
+/**
+ * @name ME_MCTL register bits definitions
+ * @{
+ */
+#define SPC5_ME_MCTL_KEY 0x5AF0U
+#define SPC5_ME_MCTL_KEY_INV 0xA50FU
+#define SPC5_ME_MCTL_MODE_MASK (15U << 28)
+#define SPC5_ME_MCTL_MODE(n) ((n) << 28)
+/** @} */
+
+/**
+ * @name ME_RUN_PCx registers bits definitions
+ * @{
+ */
+#define SPC5_ME_RUN_PC_TEST (1U << 1)
+#define SPC5_ME_RUN_PC_SAFE (1U << 2)
+#define SPC5_ME_RUN_PC_DRUN (1U << 3)
+#define SPC5_ME_RUN_PC_RUN0 (1U << 4)
+#define SPC5_ME_RUN_PC_RUN1 (1U << 5)
+#define SPC5_ME_RUN_PC_RUN2 (1U << 6)
+#define SPC5_ME_RUN_PC_RUN3 (1U << 7)
+/** @} */
+
+/**
+ * @name ME_LP_PCx registers bits definitions
+ * @{
+ */
+#define SPC5_ME_LP_PC_HALT0 (1U << 8)
+#define SPC5_ME_LP_PC_STOP0 (1U << 10)
+#define SPC5_ME_LP_PC_STANDBY0 (1U << 13)
+/** @} */
+
+/**
+ * @name ME_PCTL registers bits definitions
+ * @{
+ */
+#define SPC5_ME_PCTL_RUN_MASK (7U << 0)
+#define SPC5_ME_PCTL_RUN(n) ((n) << 0)
+#define SPC5_ME_PCTL_LP_MASK (7U << 3)
+#define SPC5_ME_PCTL_LP(n) ((n) << 3)
+#define SPC5_ME_PCTL_DBG (1U << 6)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Disables the clocks initialization in the HAL.
+ */
+#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
+#define SPC5_NO_INIT FALSE
+#endif
+
+/**
+ * @brief Disables the overclock checks.
+ */
+#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
+#define SPC5_ALLOW_OVERCLOCK FALSE
+#endif
+
+/**
+ * @brief Disables the watchdog on start.
+ */
+#if !defined(SPC5_DISABLE_WATCHDOG) || defined(__DOXYGEN__)
+#define SPC5_DISABLE_WATCHDOG TRUE
+#endif
+
+/**
+ * @brief FMPLL0 IDF divider value.
+ * @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
+ */
+#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_IDF_VALUE 1
+#endif
+
+/**
+ * @brief FMPLL0 NDIV divider value.
+ * @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
+ */
+#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_NDIV_VALUE 32
+#endif
+
+/**
+ * @brief FMPLL0 ODF divider value.
+ * @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
+ */
+#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
+#endif
+
+/**
+ * @brief XOSC divider value.
+ * @note The allowed range is 1...32.
+ */
+#if !defined(SPC5_XOSCDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_XOSCDIV_VALUE 1
+#endif
+
+/**
+ * @brief Fast IRC divider value.
+ * @note The allowed range is 1...32.
+ */
+#if !defined(SPC5_IRCDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_IRCDIV_VALUE 1
+#endif
+
+/**
+ * @brief Peripherals Set 1 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PERIPHERAL1_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief Peripherals Set 2 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PERIPHERAL2_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief Peripherals Set 3 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PERIPHERAL3_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief Active run modes in ME_ME register.
+ * @note Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
+ * is no need to specify them.
+ */
+#if !defined(SPC5_ME_ME_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \
+ SPC5_ME_ME_RUN2 | \
+ SPC5_ME_ME_RUN3 | \
+ SPC5_ME_ME_HALT0 | \
+ SPC5_ME_ME_STOP0 | \
+ SPC5_ME_ME_STANDBY0)
+#endif
+
+/**
+ * @brief TEST mode settings.
+ */
+#if !defined(SPC5_ME_TEST_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief SAFE mode settings.
+ */
+#if !defined(SPC5_ME_SAFE_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO)
+#endif
+
+/**
+ * @brief DRUN mode settings.
+ */
+#if !defined(SPC5_ME_DRUN_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN0 mode settings.
+ */
+#if !defined(SPC5_ME_RUN0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN1 mode settings.
+ */
+#if !defined(SPC5_ME_RUN1_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN2 mode settings.
+ */
+#if !defined(SPC5_ME_RUN2_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN3 mode settings.
+ */
+#if !defined(SPC5_ME_RUN3_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief HALT0 mode settings.
+ */
+#if !defined(SPC5_ME_HALT0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief STOP0 mode settings.
+ */
+#if !defined(SPC5_ME_STOP0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief STANDBY0 mode settings.
+ */
+#if !defined(SPC5_ME_STANDBY0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_STANDBY0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief Peripheral mode 0 (run mode).
+ * @note Do not change this setting, it is expected to be the "never run"
+ * mode.
+ */
+#if !defined(SPC5_ME_RUN_PC0_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC0_BITS 0
+#endif
+
+/**
+ * @brief Peripheral mode 1 (run mode).
+ * @note Do not change this setting, it is expected to be the "always run"
+ * mode.
+ */
+#if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \
+ SPC5_ME_RUN_PC_SAFE | \
+ SPC5_ME_RUN_PC_DRUN | \
+ SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 2 (run mode).
+ * @note Do not change this setting, it is expected to be the "only during
+ * normal run" mode.
+ */
+#if !defined(SPC5_ME_RUN_PC2_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \
+ SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 3 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC3_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 4 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC4_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 5 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC5_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 6 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC6_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 7 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC7_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 0 (low power mode).
+ * @note Do not change this setting, it is expected to be the "never run"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC0_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC0_BITS 0
+#endif
+
+/**
+ * @brief Peripheral mode 1 (low power mode).
+ * @note Do not change this setting, it is expected to be the "always run"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0 | \
+ SPC5_ME_LP_PC_STANDBY0)
+#endif
+
+/**
+ * @brief Peripheral mode 2 (low power mode).
+ * @note Do not change this setting, it is expected to be the "halt only"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC2_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0)
+#endif
+
+/**
+ * @brief Peripheral mode 3 (low power mode).
+ * @note Do not change this setting, it is expected to be the "stop only"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC3_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 4 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC4_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 5 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC5_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 6 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC6_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 7 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC7_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief PIT channel 0 IRQ priority.
+ * @note This PIT channel is allocated permanently for system tick
+ * generation.
+ */
+#if !defined(SPC5_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_PIT0_IRQ_PRIORITY 4
+#endif
+
+/**
+ * @brief Clock initialization failure hook.
+ * @note The default is to stop the system and let the RTC restart it.
+ * @note The hook code must not return.
+ */
+#if !defined(SPC5_CLOCK_FAILURE_HOOK) || defined(__DOXYGEN__)
+#define SPC5_CLOCK_FAILURE_HOOK() osalSysHalt("clock failure")
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(SPC560Bxx_MCUCONF)
+#error "Using a wrong mcuconf.h file, SPC560Bxx_MCUCONF not defined"
+#endif
+
+/* Check on the XOSC frequency.*/
+#if (SPC5_XOSC_CLK < SPC5_XOSC_CLK_MIN) || \
+ (SPC5_XOSC_CLK > SPC5_XOSC_CLK_MAX)
+#error "invalid SPC5_XOSC_CLK value specified"
+#endif
+
+/* Check on the XOSC divider.*/
+#if (SPC5_XOSCDIV_VALUE < 1) || (SPC5_XOSCDIV_VALUE > 32)
+#error "invalid SPC5_XOSCDIV_VALUE value specified"
+#endif
+
+/* Check on the IRC divider.*/
+#if (SPC5_IRCDIV_VALUE < 1) || (SPC5_IRCDIV_VALUE > 32)
+#error "invalid SPC5_IRCDIV_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_IDF_VALUE.*/
+#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15)
+#error "invalid SPC5_FMPLL0_IDF_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_NDIV_VALUE.*/
+#if (SPC5_FMPLL0_NDIV_VALUE < 32) || (SPC5_FMPLL0_NDIV_VALUE > 96)
+#error "invalid SPC5_FMPLL0_NDIV_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_ODF.*/
+#if (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV2)
+#define SPC5_FMPLL0_ODF_VALUE 2
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV4)
+#define SPC5_FMPLL0_ODF_VALUE 4
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV8)
+#define SPC5_FMPLL0_ODF_VALUE 8
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV16)
+#define SPC5_FMPLL0_ODF_VALUE 16
+#else
+#error "invalid SPC5_FMPLL0_ODF value specified"
+#endif
+
+/**
+ * @brief SPC5_FMPLL0_VCO_CLK clock point.
+ */
+#define SPC5_FMPLL0_VCO_CLK \
+ ((SPC5_XOSC_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE)
+
+/* Check on FMPLL0 VCO output.*/
+#if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) || \
+ (SPC5_FMPLL0_VCO_CLK > SPC5_FMPLLVCO_MAX)
+#error "SPC5_FMPLL0_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)"
+#endif
+
+/**
+ * @brief SPC5_FMPLL0_CLK clock point.
+ */
+#define SPC5_FMPLL0_CLK \
+ (SPC5_FMPLL0_VCO_CLK / SPC5_FMPLL0_ODF_VALUE)
+
+/* Check on SPC5_FMPLL0_CLK.*/
+#if (SPC5_FMPLL0_CLK > SPC5_FMPLL0_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
+#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
+#endif
+
+/* Check on the peripherals set 1 clock divider settings.*/
+#if SPC5_PERIPHERAL1_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC0 0
+#elif (SPC5_PERIPHERAL1_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PERIPHERAL1_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC0 (0x80 | (SPC5_PERIPHERAL1_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PERIPHERAL1_CLK_DIV_VALUE value specified"
+#endif
+
+/* Check on the peripherals set 2 clock divider settings.*/
+#if SPC5_PERIPHERAL2_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC1 0
+#elif (SPC5_PERIPHERAL2_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PERIPHERAL2_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC1 (0x80 | (SPC5_PERIPHERAL2_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PERIPHERAL2_CLK_DIV_VALUE value specified"
+#endif
+
+/* Check on the peripherals set 3 clock divider settings.*/
+#if SPC5_PERIPHERAL3_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC2 0
+#elif (SPC5_PERIPHERAL3_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PERIPHERAL3_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC2 (0x80 | (SPC5_PERIPHERAL3_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PERIPHERAL3_CLK_DIV_VALUE value specified"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+typedef enum {
+ SPC5_RUNMODE_TEST = 1,
+ SPC5_RUNMODE_SAFE = 2,
+ SPC5_RUNMODE_DRUN = 3,
+ SPC5_RUNMODE_RUN0 = 4,
+ SPC5_RUNMODE_RUN1 = 5,
+ SPC5_RUNMODE_RUN2 = 6,
+ SPC5_RUNMODE_RUN3 = 7,
+ SPC5_RUNMODE_HALT0 = 8,
+ SPC5_RUNMODE_STOP0 = 10
+} spc5_runmode_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#include "spc5_edma.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void spc_clock_init(void);
+ bool halSPCSetRunMode(spc5_runmode_t mode);
+ void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl);
+#if !SPC5_NO_INIT
+ uint32_t halSPCGetSystemClock(void);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560Bxx/platform.mk b/os/hal/ports/SPC5/SPC560Bxx/platform.mk new file mode 100644 index 000000000..4621464ec --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Bxx/platform.mk @@ -0,0 +1,22 @@ +# List of all the SPC560Bxx platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/SPC5/SPC560Bxx/hal_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/EDMA_v1/spc5_edma.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/ADC_v1/hal_adc_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS_v1/spc5_emios.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS_v1/hal_icu_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS_v1/hal_pwm_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/FlexCAN_v1/hal_can_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/SIUL_v1/hal_pal_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/LINFlex_v1/hal_serial_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/DSPI_v1/hal_spi_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/STM_v1/hal_st_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/SPC5/SPC560Bxx \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/EDMA_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/FlexCAN_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/SIUL_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/LINFlex_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/DSPI_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/STM_v1
diff --git a/os/hal/ports/SPC5/SPC560Bxx/registers.h b/os/hal/ports/SPC5/SPC560Bxx/registers.h new file mode 100644 index 000000000..0ea75e6c0 --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Bxx/registers.h @@ -0,0 +1,60 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file registers.h
+ * @brief Registers wrapper header.
+ *
+ * @addtogroup REGISTERS
+ * @{
+ */
+
+#ifndef REGISTERS_H
+#define REGISTERS_H
+
+#include "xpc560b.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* REGISTERS_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560Bxx/spc5_registry.h b/os/hal/ports/SPC5/SPC560Bxx/spc5_registry.h new file mode 100644 index 000000000..0f0ccc6ea --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Bxx/spc5_registry.h @@ -0,0 +1,676 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Bxx/spc560b_registry.h
+ * @brief SPC560Bxx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef SPC5_REGISTRY_H
+#define SPC5_REGISTRY_H
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if defined(_SPC560B54L3_)
+#define SPC5_NUM_DSPI 3
+#define SPC5_NUM_LINFLEX 4
+#define SPC5_NUM_GPIO 77
+
+#elif defined(_SPC560B54L5_)
+#define SPC5_NUM_DSPI 5
+#define SPC5_NUM_LINFLEX 6
+#define SPC5_NUM_GPIO 121
+
+#elif defined(_SPC560B60L3_)
+#define SPC5_NUM_DSPI 3
+#define SPC5_NUM_LINFLEX 6
+#define SPC5_NUM_GPIO 77
+
+#elif defined(_SPC560B60L5_)
+#define SPC5_NUM_DSPI 5
+#define SPC5_NUM_LINFLEX 6
+#define SPC5_NUM_GPIO 121
+
+#elif defined(_SPC560B60L7_)
+#define SPC5_NUM_DSPI 6
+#define SPC5_NUM_LINFLEX 8
+#define SPC5_NUM_GPIO 149
+
+#elif defined(_SPC560B64L5_)
+#define SPC5_NUM_DSPI 5
+#define SPC5_NUM_LINFLEX 8
+#define SPC5_NUM_GPIO 149
+
+#elif defined(_SPC560B64L7_)
+#define SPC5_NUM_DSPI 6
+#define SPC5_NUM_LINFLEX 10
+#define SPC5_NUM_GPIO 149
+
+#else
+#error "SPC560Bxx platform not defined"
+#endif
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name SPC560Bxx capabilities
+ * @{
+ */
+/* DSPI attribures.*/
+#define SPC5_DSPI_FIFO_DEPTH 4
+
+#if SPC5_NUM_DSPI > 0
+#define SPC5_HAS_DSPI0 TRUE
+#define SPC5_DSPI0_PCTL 4
+#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
+#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI0_RX_DMA_DEV_ID 2
+#define SPC5_DSPI0_TFFF_HANDLER vector76
+#define SPC5_DSPI0_TFFF_NUMBER 76
+#define SPC5_DSPI0_RFDF_HANDLER vector78
+#define SPC5_DSPI0_RFDF_NUMBER 78
+#define SPC5_DSPI0_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_START_PCTL)
+#define SPC5_DSPI0_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI0 FALSE
+#endif
+
+#if SPC5_NUM_DSPI > 1
+#define SPC5_HAS_DSPI1 TRUE
+#define SPC5_DSPI1_PCTL 5
+#define SPC5_DSPI1_TX1_DMA_DEV_ID 3
+#define SPC5_DSPI1_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI1_RX_DMA_DEV_ID 4
+#define SPC5_DSPI1_TFFF_HANDLER vector96
+#define SPC5_DSPI1_TFFF_NUMBER 96
+#define SPC5_DSPI1_RFDF_HANDLER vector98
+#define SPC5_DSPI1_RFDF_NUMBER 98
+#define SPC5_DSPI1_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_START_PCTL)
+#define SPC5_DSPI1_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI1 FALSE
+#endif
+
+#if SPC5_NUM_DSPI > 2
+#define SPC5_HAS_DSPI2 TRUE
+#define SPC5_DSPI2_PCTL 6
+#define SPC5_DSPI2_TX1_DMA_DEV_ID 5
+#define SPC5_DSPI2_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI2_RX_DMA_DEV_ID 6
+#define SPC5_DSPI2_TFFF_HANDLER vector116
+#define SPC5_DSPI2_TFFF_NUMBER 116
+#define SPC5_DSPI2_RFDF_HANDLER vector118
+#define SPC5_DSPI2_RFDF_NUMBER 118
+#define SPC5_DSPI2_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_START_PCTL)
+#define SPC5_DSPI2_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI2 FALSE
+#endif
+
+#if SPC5_NUM_DSPI > 3
+#define SPC5_HAS_DSPI3 TRUE
+#define SPC5_DSPI3_PCTL 7
+#define SPC5_DSPI3_TX1_DMA_DEV_ID 7
+#define SPC5_DSPI3_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI3_RX_DMA_DEV_ID 8
+#define SPC5_DSPI3_TFFF_HANDLER vector184
+#define SPC5_DSPI3_TFFF_NUMBER 184
+#define SPC5_DSPI3_RFDF_HANDLER vector186
+#define SPC5_DSPI3_RFDF_NUMBER 186
+#define SPC5_DSPI3_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI3_PCTL, SPC5_SPI_DSPI3_START_PCTL)
+#define SPC5_DSPI3_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI3_PCTL, SPC5_SPI_DSPI3_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI3 FALSE
+#endif
+
+#if SPC5_NUM_DSPI > 4
+#define SPC5_HAS_DSPI4 TRUE
+#define SPC5_DSPI4_PCTL 8
+#define SPC5_DSPI4_TX1_DMA_DEV_ID 9
+#define SPC5_DSPI4_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI4_RX_DMA_DEV_ID 10
+#define SPC5_DSPI4_TFFF_HANDLER vector213
+#define SPC5_DSPI4_TFFF_NUMBER 213
+#define SPC5_DSPI4_RFDF_HANDLER vector215
+#define SPC5_DSPI4_RFDF_NUMBER 215
+#define SPC5_DSPI4_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI4_PCTL, SPC5_SPI_DSPI4_START_PCTL)
+#define SPC5_DSPI4_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI4_PCTL, SPC5_SPI_DSPI4_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI4 FALSE
+#endif
+
+#if SPC5_NUM_DSPI > 5
+#define SPC5_HAS_DSPI5 TRUE
+#define SPC5_DSPI5_PCTL 9
+#define SPC5_DSPI5_TX1_DMA_DEV_ID 11
+#define SPC5_DSPI5_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI5_RX_DMA_DEV_ID 12
+#define SPC5_DSPI5_TFFF_HANDLER vector221
+#define SPC5_DSPI5_TFFF_NUMBER 221
+#define SPC5_DSPI5_RFDF_HANDLER vector223
+#define SPC5_DSPI5_RFDF_NUMBER 223
+#define SPC5_DSPI5_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI5_PCTL, SPC5_SPI_DSPI5_START_PCTL)
+#define SPC5_DSPI5_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI5_PCTL, SPC5_SPI_DSPI5_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI5 FALSE
+#endif
+
+#define SPC5_HAS_DSPI6 FALSE
+#define SPC5_HAS_DSPI7 FALSE
+
+/* eDMA attributes.*/
+#define SPC5_HAS_EDMA TRUE
+#define SPC5_EDMA_NCHANNELS 16
+#define SPC5_EDMA_HAS_MUX TRUE
+#define SPC5_EDMA_MUX_PCTL 23
+
+/* LINFlex attributes.*/
+#if SPC5_NUM_LINFLEX > 0
+#define SPC5_HAS_LINFLEX0 TRUE
+#define SPC5_LINFLEX0_PCTL 48
+#define SPC5_LINFLEX0_RXI_HANDLER vector79
+#define SPC5_LINFLEX0_TXI_HANDLER vector80
+#define SPC5_LINFLEX0_ERR_HANDLER vector81
+#define SPC5_LINFLEX0_RXI_NUMBER 79
+#define SPC5_LINFLEX0_TXI_NUMBER 80
+#define SPC5_LINFLEX0_ERR_NUMBER 81
+#define SPC5_LINFLEX0_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX0 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 1
+#define SPC5_HAS_LINFLEX1 TRUE
+#define SPC5_LINFLEX1_PCTL 49
+#define SPC5_LINFLEX1_RXI_HANDLER vector99
+#define SPC5_LINFLEX1_TXI_HANDLER vector100
+#define SPC5_LINFLEX1_ERR_HANDLER vector101
+#define SPC5_LINFLEX1_RXI_NUMBER 99
+#define SPC5_LINFLEX1_TXI_NUMBER 100
+#define SPC5_LINFLEX1_ERR_NUMBER 101
+#define SPC5_LINFLEX1_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX1 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 2
+#define SPC5_HAS_LINFLEX2 TRUE
+#define SPC5_LINFLEX2_PCTL 50
+#define SPC5_LINFLEX2_RXI_HANDLER vector119
+#define SPC5_LINFLEX2_TXI_HANDLER vector120
+#define SPC5_LINFLEX2_ERR_HANDLER vector121
+#define SPC5_LINFLEX2_RXI_NUMBER 119
+#define SPC5_LINFLEX2_TXI_NUMBER 120
+#define SPC5_LINFLEX2_ERR_NUMBER 121
+#define SPC5_LINFLEX2_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX2 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 3
+#define SPC5_HAS_LINFLEX3 TRUE
+#define SPC5_LINFLEX3_PCTL 51
+#define SPC5_LINFLEX3_RXI_HANDLER vector122
+#define SPC5_LINFLEX3_TXI_HANDLER vector123
+#define SPC5_LINFLEX3_ERR_HANDLER vector124
+#define SPC5_LINFLEX3_RXI_NUMBER 122
+#define SPC5_LINFLEX3_TXI_NUMBER 123
+#define SPC5_LINFLEX3_ERR_NUMBER 124
+#define SPC5_LINFLEX3_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX3 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 4
+#define SPC5_HAS_LINFLEX4 TRUE
+#define SPC5_LINFLEX4_PCTL 52
+#define SPC5_LINFLEX4_RXI_HANDLER vector187
+#define SPC5_LINFLEX4_TXI_HANDLER vector188
+#define SPC5_LINFLEX4_ERR_HANDLER vector189
+#define SPC5_LINFLEX4_RXI_NUMBER 187
+#define SPC5_LINFLEX4_TXI_NUMBER 188
+#define SPC5_LINFLEX4_ERR_NUMBER 189
+#define SPC5_LINFLEX4_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX4 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 5
+#define SPC5_HAS_LINFLEX5 TRUE
+#define SPC5_LINFLEX5_PCTL 53
+#define SPC5_LINFLEX5_RXI_HANDLER vector199
+#define SPC5_LINFLEX5_TXI_HANDLER vector200
+#define SPC5_LINFLEX5_ERR_HANDLER vector201
+#define SPC5_LINFLEX5_RXI_NUMBER 199
+#define SPC5_LINFLEX5_TXI_NUMBER 200
+#define SPC5_LINFLEX5_ERR_NUMBER 201
+#define SPC5_LINFLEX5_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX5 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 6
+#define SPC5_HAS_LINFLEX6 TRUE
+#define SPC5_LINFLEX6_PCTL 54
+#define SPC5_LINFLEX6_RXI_HANDLER vector216
+#define SPC5_LINFLEX6_TXI_HANDLER vector217
+#define SPC5_LINFLEX6_ERR_HANDLER vector218
+#define SPC5_LINFLEX6_RXI_NUMBER 216
+#define SPC5_LINFLEX6_TXI_NUMBER 217
+#define SPC5_LINFLEX6_ERR_NUMBER 218
+#define SPC5_LINFLEX6_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX6 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 7
+#define SPC5_HAS_LINFLEX7 TRUE
+#define SPC5_LINFLEX7_PCTL 55
+#define SPC5_LINFLEX7_RXI_HANDLER vector224
+#define SPC5_LINFLEX7_TXI_HANDLER vector225
+#define SPC5_LINFLEX7_ERR_HANDLER vector226
+#define SPC5_LINFLEX7_RXI_NUMBER 224
+#define SPC5_LINFLEX7_TXI_NUMBER 225
+#define SPC5_LINFLEX7_ERR_NUMBER 226
+#define SPC5_LINFLEX7_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX7 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 8
+#define SPC5_HAS_LINFLEX8 TRUE
+#define SPC5_LINFLEX8_PCTL 12
+#define SPC5_LINFLEX8_RXI_HANDLER vector227
+#define SPC5_LINFLEX8_TXI_HANDLER vector228
+#define SPC5_LINFLEX8_ERR_HANDLER vector229
+#define SPC5_LINFLEX8_RXI_NUMBER 227
+#define SPC5_LINFLEX8_TXI_NUMBER 228
+#define SPC5_LINFLEX8_ERR_NUMBER 229
+#define SPC5_LINFLEX8_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX8 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 9
+#define SPC5_HAS_LINFLEX9 TRUE
+#define SPC5_LINFLEX9_PCTL 13
+#define SPC5_LINFLEX9_RXI_HANDLER vector230
+#define SPC5_LINFLEX9_TXI_HANDLER vector231
+#define SPC5_LINFLEX9_ERR_HANDLER vector232
+#define SPC5_LINFLEX9_RXI_NUMBER 230
+#define SPC5_LINFLEX9_TXI_NUMBER 231
+#define SPC5_LINFLEX9_ERR_NUMBER 232
+#define SPC5_LINFLEX9_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX9 FALSE
+#endif
+
+/* SIUL attributes.*/
+#define SPC5_HAS_SIUL TRUE
+#define SPC5_SIUL_PCTL 68
+#define SPC5_SIUL_NUM_PORTS 10
+#define SPC5_SIUL_NUM_PCRS 149
+#define SPC5_SIUL_NUM_PADSELS 64
+#define SPC5_SIUL_SYSTEM_PINS 32,33,121,122
+
+/* eMIOS attributes.*/
+#define SPC5_HAS_EMIOS0 TRUE
+#define SPC5_EMIOS0_PCTL 72
+#define SPC5_EMIOS0_GFR_F0F1_HANDLER vector141
+#define SPC5_EMIOS0_GFR_F2F3_HANDLER vector142
+#define SPC5_EMIOS0_GFR_F4F5_HANDLER vector143
+#define SPC5_EMIOS0_GFR_F6F7_HANDLER vector144
+#define SPC5_EMIOS0_GFR_F8F9_HANDLER vector145
+#define SPC5_EMIOS0_GFR_F10F11_HANDLER vector146
+#define SPC5_EMIOS0_GFR_F12F13_HANDLER vector147
+#define SPC5_EMIOS0_GFR_F14F15_HANDLER vector148
+#define SPC5_EMIOS0_GFR_F16F17_HANDLER vector149
+#define SPC5_EMIOS0_GFR_F18F19_HANDLER vector150
+#define SPC5_EMIOS0_GFR_F20F21_HANDLER vector151
+#define SPC5_EMIOS0_GFR_F22F23_HANDLER vector152
+#define SPC5_EMIOS0_GFR_F24F25_HANDLER vector153
+#define SPC5_EMIOS0_GFR_F26F27_HANDLER vector154
+#define SPC5_EMIOS0_GFR_F0F1_NUMBER 141
+#define SPC5_EMIOS0_GFR_F2F3_NUMBER 142
+#define SPC5_EMIOS0_GFR_F4F5_NUMBER 143
+#define SPC5_EMIOS0_GFR_F6F7_NUMBER 144
+#define SPC5_EMIOS0_GFR_F8F9_NUMBER 145
+#define SPC5_EMIOS0_GFR_F10F11_NUMBER 146
+#define SPC5_EMIOS0_GFR_F12F13_NUMBER 147
+#define SPC5_EMIOS0_GFR_F14F15_NUMBER 148
+#define SPC5_EMIOS0_GFR_F16F17_NUMBER 149
+#define SPC5_EMIOS0_GFR_F18F19_NUMBER 150
+#define SPC5_EMIOS0_GFR_F20F21_NUMBER 151
+#define SPC5_EMIOS0_GFR_F22F23_NUMBER 152
+#define SPC5_EMIOS0_GFR_F24F25_NUMBER 153
+#define SPC5_EMIOS0_GFR_F26F27_NUMBER 154
+
+#define SPC5_EMIOS0_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL3_CLK_DIV_VALUE / \
+ SPC5_EMIOS0_GPRE_VALUE)
+
+#define SPC5_HAS_EMIOS1 TRUE
+#define SPC5_EMIOS1_PCTL 73
+#define SPC5_EMIOS1_GFR_F0F1_HANDLER vector157
+#define SPC5_EMIOS1_GFR_F2F3_HANDLER vector158
+#define SPC5_EMIOS1_GFR_F4F5_HANDLER vector159
+#define SPC5_EMIOS1_GFR_F6F7_HANDLER vector160
+#define SPC5_EMIOS1_GFR_F8F9_HANDLER vector161
+#define SPC5_EMIOS1_GFR_F10F11_HANDLER vector162
+#define SPC5_EMIOS1_GFR_F12F13_HANDLER vector163
+#define SPC5_EMIOS1_GFR_F14F15_HANDLER vector164
+#define SPC5_EMIOS1_GFR_F16F17_HANDLER vector165
+#define SPC5_EMIOS1_GFR_F18F19_HANDLER vector166
+#define SPC5_EMIOS1_GFR_F20F21_HANDLER vector167
+#define SPC5_EMIOS1_GFR_F22F23_HANDLER vector168
+#define SPC5_EMIOS1_GFR_F24F25_HANDLER vector169
+#define SPC5_EMIOS1_GFR_F26F27_HANDLER vector170
+#define SPC5_EMIOS1_GFR_F0F1_NUMBER 157
+#define SPC5_EMIOS1_GFR_F2F3_NUMBER 158
+#define SPC5_EMIOS1_GFR_F4F5_NUMBER 159
+#define SPC5_EMIOS1_GFR_F6F7_NUMBER 160
+#define SPC5_EMIOS1_GFR_F8F9_NUMBER 161
+#define SPC5_EMIOS1_GFR_F10F11_NUMBER 162
+#define SPC5_EMIOS1_GFR_F12F13_NUMBER 163
+#define SPC5_EMIOS1_GFR_F14F15_NUMBER 164
+#define SPC5_EMIOS1_GFR_F16F17_NUMBER 165
+#define SPC5_EMIOS1_GFR_F18F19_NUMBER 166
+#define SPC5_EMIOS1_GFR_F20F21_NUMBER 167
+#define SPC5_EMIOS1_GFR_F22F23_NUMBER 168
+#define SPC5_EMIOS1_GFR_F24F25_NUMBER 169
+#define SPC5_EMIOS1_GFR_F26F27_NUMBER 170
+
+#define SPC5_EMIOS1_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL3_CLK_DIV_VALUE / \
+ SPC5_EMIOS1_GPRE_VALUE)
+
+/* FlexCAN attributes.*/
+#define SPC5_HAS_FLEXCAN0 TRUE
+#define SPC5_FLEXCAN0_PCTL 16
+#define SPC5_FLEXCAN0_MB 64
+#define SPC5_FLEXCAN0_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER vector69
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER vector70
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER vector71
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector72
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER vector73
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 65
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 66
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER 68
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER 69
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER 70
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_NUMBER 73
+#define SPC5_FLEXCAN0_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_START_PCTL);
+#define SPC5_FLEXCAN0_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_STOP_PCTL);
+
+#define SPC5_HAS_FLEXCAN1 TRUE
+#define SPC5_FLEXCAN1_PCTL 17
+#define SPC5_FLEXCAN1_MB 64
+#define SPC5_FLEXCAN1_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER vector85
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER vector86
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER vector88
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER vector89
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER vector90
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER vector91
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER vector92
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_HANDLER vector93
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER 85
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER 86
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER 88
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER 89
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER 90
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER 91
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER 92
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_NUMBER 93
+#define SPC5_FLEXCAN1_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_START_PCTL);
+#define SPC5_FLEXCAN1_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_STOP_PCTL);
+
+#define SPC5_HAS_FLEXCAN2 TRUE
+#define SPC5_FLEXCAN2_PCTL 18
+#define SPC5_FLEXCAN2_MB 64
+#define SPC5_FLEXCAN2_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER vector105
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER vector106
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_HANDLER vector108
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_HANDLER vector109
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_HANDLER vector110
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_HANDLER vector111
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_HANDLER vector112
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_HANDLER vector113
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_NUMBER 105
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_NUMBER 106
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_NUMBER 108
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_NUMBER 109
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_NUMBER 110
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_NUMBER 111
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER 112
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_NUMBER 113
+#define SPC5_FLEXCAN2_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL);
+#define SPC5_FLEXCAN2_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL);
+
+#define SPC5_HAS_FLEXCAN3 TRUE
+#define SPC5_FLEXCAN3_PCTL 19
+#define SPC5_FLEXCAN3_MB 64
+#define SPC5_FLEXCAN3_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_HANDLER vector173
+#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_HANDLER vector174
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_HANDLER vector176
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_HANDLER vector177
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_HANDLER vector178
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_HANDLER vector179
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_HANDLER vector180
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_HANDLER vector181
+#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_NUMBER 173
+#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_NUMBER 174
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_NUMBER 176
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_NUMBER 177
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_NUMBER 178
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_NUMBER 179
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_NUMBER 180
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_NUMBER 181
+#define SPC5_FLEXCAN3_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, SPC5_CAN_FLEXCAN3_START_PCTL);
+#define SPC5_FLEXCAN3_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, SPC5_CAN_FLEXCAN3_STOP_PCTL);
+
+#define SPC5_HAS_FLEXCAN4 TRUE
+#define SPC5_FLEXCAN4_PCTL 20
+#define SPC5_FLEXCAN4_MB 64
+#define SPC5_FLEXCAN4_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_HANDLER vector190
+#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_HANDLER vector191
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_HANDLER vector193
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_HANDLER vector194
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_HANDLER vector195
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_HANDLER vector196
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_HANDLER vector197
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_HANDLER vector198
+#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_NUMBER 190
+#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_NUMBER 191
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_NUMBER 193
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_NUMBER 194
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_NUMBER 195
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_NUMBER 196
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_NUMBER 197
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_NUMBER 198
+#define SPC5_FLEXCAN4_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, SPC5_CAN_FLEXCAN4_START_PCTL);
+#define SPC5_FLEXCAN4_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, SPC5_CAN_FLEXCAN4_STOP_PCTL);
+
+#define SPC5_HAS_FLEXCAN5 TRUE
+#define SPC5_FLEXCAN5_PCTL 21
+#define SPC5_FLEXCAN5_MB 64
+#define SPC5_FLEXCAN5_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_HANDLER vector202
+#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_HANDLER vector203
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_HANDLER vector205
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_HANDLER vector206
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_HANDLER vector207
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_HANDLER vector208
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_HANDLER vector209
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_HANDLER vector210
+#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_NUMBER 202
+#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_NUMBER 203
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_NUMBER 205
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_NUMBER 206
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_NUMBER 207
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_NUMBER 208
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_NUMBER 209
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_NUMBER 210
+#define SPC5_FLEXCAN5_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, SPC5_CAN_FLEXCAN5_START_PCTL);
+#define SPC5_FLEXCAN5_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, SPC5_CAN_FLEXCAN5_STOP_PCTL);
+
+/* ADC attributes.*/
+#define SPC5_ADC_HAS_TRC FALSE
+
+#define SPC5_HAS_ADC0 TRUE
+#define SPC5_ADC_ADC0_HAS_CTR0 TRUE
+#define SPC5_ADC_ADC0_HAS_CTR1 TRUE
+#define SPC5_ADC_ADC0_HAS_CTR2 TRUE
+#define SPC5_ADC_ADC0_HAS_NCMR0 TRUE
+#define SPC5_ADC_ADC0_HAS_NCMR1 TRUE
+#define SPC5_ADC_ADC0_HAS_NCMR2 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR0 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR1 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR2 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR3 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR4 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR5 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR6 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR7 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR8 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR9 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR10 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR11 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR12 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR13 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR14 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR15 FALSE
+#define SPC5_ADC_ADC0_HAS_CWENR0 TRUE
+#define SPC5_ADC_ADC0_HAS_CWENR1 TRUE
+#define SPC5_ADC_ADC0_HAS_CWENR2 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL0 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL1 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL2 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL3 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL4 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL5 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL6 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL7 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL8 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL9 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL10 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL11 TRUE
+#define SPC5_ADC_ADC0_HAS_CIMR0 TRUE
+#define SPC5_ADC_ADC0_HAS_CIMR1 TRUE
+#define SPC5_ADC_ADC0_HAS_CIMR2 TRUE
+#define SPC5_ADC_ADC0_HAS_CEOCFR0 TRUE
+#define SPC5_ADC_ADC0_HAS_CEOCFR1 TRUE
+#define SPC5_ADC_ADC0_HAS_CEOCFR2 TRUE
+#define SPC5_ADC0_PCTL 32
+#define SPC5_ADC0_DMA_DEV_ID 29
+#define SPC5_ADC0_EOC_HANDLER vector62
+#define SPC5_ADC0_EOC_NUMBER 62
+#define SPC5_ADC0_WD_HANDLER vector64
+#define SPC5_ADC0_WD_NUMBER 64
+
+#define SPC5_HAS_ADC1 TRUE
+#define SPC5_ADC_ADC1_HAS_CTR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CTR1 TRUE
+#define SPC5_ADC_ADC1_HAS_CTR2 FALSE
+#define SPC5_ADC_ADC1_HAS_NCMR0 TRUE
+#define SPC5_ADC_ADC1_HAS_NCMR1 TRUE
+#define SPC5_ADC_ADC1_HAS_NCMR2 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR0 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR1 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR2 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR3 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR4 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR5 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR6 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR7 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR8 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR9 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR10 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR11 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR12 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR13 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR14 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR15 FALSE
+#define SPC5_ADC_ADC1_HAS_CWENR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CWENR1 TRUE
+#define SPC5_ADC_ADC1_HAS_CWENR2 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL0 TRUE
+#define SPC5_ADC_ADC1_HAS_CWSEL1 TRUE
+#define SPC5_ADC_ADC1_HAS_CWSEL2 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL3 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL4 TRUE
+#define SPC5_ADC_ADC1_HAS_CWSEL5 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL6 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL7 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL8 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL9 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL10 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL11 FALSE
+#define SPC5_ADC_ADC1_HAS_CIMR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CIMR1 TRUE
+#define SPC5_ADC_ADC1_HAS_CIMR2 TRUE
+#define SPC5_ADC_ADC1_HAS_CEOCFR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CEOCFR1 TRUE
+#define SPC5_ADC_ADC1_HAS_CEOCFR2 TRUE
+#define SPC5_ADC1_PCTL 33
+#define SPC5_ADC1_DMA_DEV_ID 30
+#define SPC5_ADC1_EOC_HANDLER vector82
+#define SPC5_ADC1_EOC_NUMBER 82
+#define SPC5_ADC1_WD_HANDLER vector84
+#define SPC5_ADC1_WD_NUMBER 84
+/** @} */
+
+#endif /* SPC5_REGISTRY_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560Bxx/typedefs.h b/os/hal/ports/SPC5/SPC560Bxx/typedefs.h new file mode 100644 index 000000000..b798a3b5c --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Bxx/typedefs.h @@ -0,0 +1,38 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Bxx/typedefs.h
+ * @brief Dummy typedefs file.
+ */
+
+#ifndef _TYPEDEFS_H_
+#define _TYPEDEFS_H_
+
+#include <stdint.h>
+
+/*
+ * Derived generic types.
+ */
+typedef volatile int8_t vint8_t; /**< Volatile signed 8 bits. */
+typedef volatile uint8_t vuint8_t; /**< Volatile unsigned 8 bits. */
+typedef volatile int16_t vint16_t; /**< Volatile signed 16 bits. */
+typedef volatile uint16_t vuint16_t; /**< Volatile unsigned 16 bits. */
+typedef volatile int32_t vint32_t; /**< Volatile signed 32 bits. */
+typedef volatile uint32_t vuint32_t; /**< Volatile unsigned 32 bits. */
+typedef volatile uint64_t vuint64_t; /**< Volatile unsigned 64 bits. */
+
+#endif /* _TYPEDEFS_H_ */
diff --git a/os/hal/ports/SPC5/SPC560Bxx/xpc560b.h b/os/hal/ports/SPC5/SPC560Bxx/xpc560b.h new file mode 100644 index 000000000..ac637b6cf --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Bxx/xpc560b.h @@ -0,0 +1,6551 @@ +/*****************************************************************
+ * PROJECT : MPC5607B
+ *
+ * FILE : jdp.h
+ *
+ * DESCRIPTION : This is the header file describing the register
+ * set for MPC5607B
+ *
+ * COPYRIGHT :(c) 2008, Freescale & STMicroelectronics
+ *
+ * VERSION : 01.03
+ * DATE : 1.20.2010
+ * AUTHOR : r23668
+ * HISTORY : Hand edited from previous jdp.h file
+ * Changes from rev 1.01
+ * CGM Section replaced with more accurate section from Bolero 512K
+ * eMIOS CADR, CBDR & CCNTR changed from 24 to 16 bit.
+ * CAN Sampler section corrected: 0-15 should be resrved not 16-32.
+ * Includes additions from Stefan Luellman
+* Example instantiation and use:
+*
+* <MODULE>.<REGISTER>.B.<BIT> = 1;
+* <MODULE>.<REGISTER>.R = 0x10000000;
+*
+******************************************************************/
+
+#ifndef _JDP_H_
+#define _JDP_H_
+
+#include "typedefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __MWERKS__
+#pragma push
+#pragma ANSI_strict off
+#endif
+
+
+/****************************************************************************/
+/* MODULE : ADC0 */
+/****************************************************************************/
+ struct ADC0_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OWREN:1;
+ vuint32_t WLSIDE:1;
+ vuint32_t MODE:1;
+ vuint32_t EDGLEV:1;
+ vuint32_t TRGEN:1;
+ vuint32_t EDGE:1;
+ vuint32_t XSTRTEN:1;
+ vuint32_t NSTART:1;
+ vuint32_t:1;
+ vuint32_t JTRGEN:1;
+ vuint32_t JEDGE:1;
+ vuint32_t JSTART:1;
+ vuint32_t:2;
+ vuint32_t CTUEN:1;
+ vuint32_t:8;
+ vuint32_t ADCLKSEL:1;
+ vuint32_t ABORT_CHAIN:1;
+ vuint32_t ABORT:1;
+ vuint32_t ACKO:1;
+ vuint32_t:1; //vuint32_t OFFREFRESH:1;
+ vuint32_t:1; //vuint32_t OFFCANC:1;
+ vuint32_t:2;
+ vuint32_t PWDN:1;
+ } B;
+ } MCR; /* MAIN CONFIGURATION REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:7;
+ vuint32_t NSTART:1;
+ vuint32_t JABORT:1;
+ vuint32_t:2;
+ vuint32_t JSTART:1;
+ vuint32_t:3;
+ vuint32_t CTUSTART:1;
+ vuint32_t CHADDR:7;
+ vuint32_t:3;
+ vuint32_t ACKO:1;
+ vuint32_t:1; //vuint32_t OFFREFRESH:1;
+ vuint32_t:1; //vuint32_t OFFCANC:1;
+ vuint32_t ADCSTATUS:3;
+ } B;
+ } MSR; /* MAIN STATUS REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC0_reserved0;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC0_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t:1; //vuint32_t OFFCANCOVR:1;
+ vuint32_t:1; //vuint32_t EOFFSET:1;
+ vuint32_t EOCTU:1;
+ vuint32_t JEOC:1;
+ vuint32_t JECH:1;
+ vuint32_t EOC:1;
+ vuint32_t ECH:1;
+ } B;
+ } ISR; /* INTERRUPT STATUS REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t EOC_CH15:1;
+ vuint32_t EOC_CH14:1;
+ vuint32_t EOC_CH13:1;
+ vuint32_t EOC_CH12:1;
+ vuint32_t EOC_CH11:1;
+ vuint32_t EOC_CH10:1;
+ vuint32_t EOC_CH9:1;
+ vuint32_t EOC_CH8:1;
+ vuint32_t EOC_CH7:1;
+ vuint32_t EOC_CH6:1;
+ vuint32_t EOC_CH5:1;
+ vuint32_t EOC_CH4:1;
+ vuint32_t EOC_CH3:1;
+ vuint32_t EOC_CH2:1;
+ vuint32_t EOC_CH1:1;
+ vuint32_t EOC_CH0:1;
+ } B;
+ } CE0CFR0; /* PRECISE CHANNELS PENDING REGISTERS */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EOC_CH31:1;
+ vuint32_t EOC_CH30:1;
+ vuint32_t EOC_CH29:1;
+ vuint32_t EOC_CH28:1;
+ vuint32_t EOC_CH27:1;
+ vuint32_t EOC_CH26:1;
+ vuint32_t EOC_CH25:1;
+ vuint32_t EOC_CH24:1;
+ vuint32_t EOC_CH23:1;
+ vuint32_t EOC_CH22:1;
+ vuint32_t EOC_CH21:1;
+ vuint32_t EOC_CH20:1;
+ vuint32_t EOC_CH19:1;
+ vuint32_t EOC_CH18:1;
+ vuint32_t EOC_CH17:1;
+ vuint32_t EOC_CH16:1;
+ vuint32_t EOC_CH15:1;
+ vuint32_t EOC_CH14:1;
+ vuint32_t EOC_CH13:1;
+ vuint32_t EOC_CH12:1;
+ vuint32_t EOC_CH11:1;
+ vuint32_t EOC_CH10:1;
+ vuint32_t EOC_CH9:1;
+ vuint32_t EOC_CH8:1;
+ vuint32_t EOC_CH7:1;
+ vuint32_t EOC_CH6:1;
+ vuint32_t EOC_CH5:1;
+ vuint32_t EOC_CH4:1;
+ vuint32_t EOC_CH3:1;
+ vuint32_t EOC_CH2:1;
+ vuint32_t EOC_CH1:1;
+ vuint32_t EOC_CH0:1;
+ } B;
+ } CE0CFR1; /* EXTENDED INTERNAL CHANNELS PENDING REGISTERS */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EOC_CH31:1;
+ vuint32_t EOC_CH30:1;
+ vuint32_t EOC_CH29:1;
+ vuint32_t EOC_CH28:1;
+ vuint32_t EOC_CH27:1;
+ vuint32_t EOC_CH26:1;
+ vuint32_t EOC_CH25:1;
+ vuint32_t EOC_CH24:1;
+ vuint32_t EOC_CH23:1;
+ vuint32_t EOC_CH22:1;
+ vuint32_t EOC_CH21:1;
+ vuint32_t EOC_CH20:1;
+ vuint32_t EOC_CH19:1;
+ vuint32_t EOC_CH18:1;
+ vuint32_t EOC_CH17:1;
+ vuint32_t EOC_CH16:1;
+ vuint32_t EOC_CH15:1;
+ vuint32_t EOC_CH14:1;
+ vuint32_t EOC_CH13:1;
+ vuint32_t EOC_CH12:1;
+ vuint32_t EOC_CH11:1;
+ vuint32_t EOC_CH10:1;
+ vuint32_t EOC_CH9:1;
+ vuint32_t EOC_CH8:1;
+ vuint32_t EOC_CH7:1;
+ vuint32_t EOC_CH6:1;
+ vuint32_t EOC_CH5:1;
+ vuint32_t EOC_CH4:1;
+ vuint32_t EOC_CH3:1;
+ vuint32_t EOC_CH2:1;
+ vuint32_t EOC_CH1:1;
+ vuint32_t EOC_CH0:1;
+ } B;
+ } CE0CFR2; /* EXTERNAL CHANNELS PENDING REGISTERS */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t:1; //vuint32_t MSKOFFCANCOVR:1;
+ vuint32_t:1; //vuint32_t MSKEOFFSET:1;
+ vuint32_t MSKEOCTU:1;
+ vuint32_t MSKJEOC:1;
+ vuint32_t MSKJECH:1;
+ vuint32_t MSKEOC:1;
+ vuint32_t MSKECH:1;
+ } B;
+ } IMR; /* INTERRUPT MASK REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CIM15:1;
+ vuint32_t CIM14:1;
+ vuint32_t CIM13:1;
+ vuint32_t CIM12:1;
+ vuint32_t CIM11:1;
+ vuint32_t CIM10:1;
+ vuint32_t CIM9:1;
+ vuint32_t CIM8:1;
+ vuint32_t CIM7:1;
+ vuint32_t CIM6:1;
+ vuint32_t CIM5:1;
+ vuint32_t CIM4:1;
+ vuint32_t CIM3:1;
+ vuint32_t CIM2:1;
+ vuint32_t CIM1:1;
+ vuint32_t CIM0:1;
+ } B;
+ } CIMR0; /* PRECISE CHANNELS INTERRUPT MASK 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CIM31:1;
+ vuint32_t CIM30:1;
+ vuint32_t CIM29:1;
+ vuint32_t CIM28:1;
+ vuint32_t CIM27:1;
+ vuint32_t CIM26:1;
+ vuint32_t CIM25:1;
+ vuint32_t CIM24:1;
+ vuint32_t CIM23:1;
+ vuint32_t CIM22:1;
+ vuint32_t CIM21:1;
+ vuint32_t CIM20:1;
+ vuint32_t CIM19:1;
+ vuint32_t CIM18:1;
+ vuint32_t CIM17:1;
+ vuint32_t CIM16:1;
+ vuint32_t CIM15:1;
+ vuint32_t CIM14:1;
+ vuint32_t CIM13:1;
+ vuint32_t CIM12:1;
+ vuint32_t CIM11:1;
+ vuint32_t CIM10:1;
+ vuint32_t CIM9:1;
+ vuint32_t CIM8:1;
+ vuint32_t CIM7:1;
+ vuint32_t CIM6:1;
+ vuint32_t CIM5:1;
+ vuint32_t CIM4:1;
+ vuint32_t CIM3:1;
+ vuint32_t CIM2:1;
+ vuint32_t CIM1:1;
+ vuint32_t CIM0:1;
+ } B;
+ } CIMR1; /* EXTENDED INTERNAL CHANNELS INTERRUPT MASK 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CIM31:1;
+ vuint32_t CIM30:1;
+ vuint32_t CIM29:1;
+ vuint32_t CIM28:1;
+ vuint32_t CIM27:1;
+ vuint32_t CIM26:1;
+ vuint32_t CIM25:1;
+ vuint32_t CIM24:1;
+ vuint32_t CIM23:1;
+ vuint32_t CIM22:1;
+ vuint32_t CIM21:1;
+ vuint32_t CIM20:1;
+ vuint32_t CIM19:1;
+ vuint32_t CIM18:1;
+ vuint32_t CIM17:1;
+ vuint32_t CIM16:1;
+ vuint32_t CIM15:1;
+ vuint32_t CIM14:1;
+ vuint32_t CIM13:1;
+ vuint32_t CIM12:1;
+ vuint32_t CIM11:1;
+ vuint32_t CIM10:1;
+ vuint32_t CIM9:1;
+ vuint32_t CIM8:1;
+ vuint32_t CIM7:1;
+ vuint32_t CIM6:1;
+ vuint32_t CIM5:1;
+ vuint32_t CIM4:1;
+ vuint32_t CIM3:1;
+ vuint32_t CIM2:1;
+ vuint32_t CIM1:1;
+ vuint32_t CIM0:1;
+ } B;
+ } CIMR2; /* EXTERNAL CHANNELS INTERRUPT MASK 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t WDG5H:1; // non validi
+ vuint32_t WDG5L:1; // non validi
+ vuint32_t WDG4H:1; // non validi
+ vuint32_t WDG4L:1; // non validi
+ vuint32_t WDG3H:1; // validi
+ vuint32_t WDG3L:1; // validi
+ vuint32_t WDG2H:1; // validi
+ vuint32_t WDG2L:1; // validi
+ vuint32_t WDG1H:1; // validi
+ vuint32_t WDG1L:1; // validi
+ vuint32_t WDG0H:1; // validi
+ vuint32_t WDG0L:1; // validi
+ } B;
+ } WTISR; /* WATCHDOG THRESHOLD INTERRUPT STATUS REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t MSKWDG5H:1; // non validi
+ vuint32_t MSKWDG5L:1; // non validi
+ vuint32_t MSKWDG4H:1; // non validi
+ vuint32_t MSKWDG4L:1; // non validi
+ vuint32_t MSKWDG3H:1; // validi
+ vuint32_t MSKWDG2H:1; // validi
+ vuint32_t MSKWDG1H:1; // validi
+ vuint32_t MSKWDG0H:1; // validi
+ vuint32_t MSKWDG3L:1; // validi
+ vuint32_t MSKWDG2L:1; // validi
+ vuint32_t MSKWDG1L:1; // validi
+ vuint32_t MSKWDG0L:1; // validi
+ } B;
+ } WTIMR; /* WATCHDOG THRESHOLD INTERRUPT MASK REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC0_reserved2;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC0_reserved3;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t DCLR:1;
+ vuint32_t DMAEN:1;
+ } B;
+ } DMAE; /* DMA ENABLE REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DMA15:1;
+ vuint32_t DMA14:1;
+ vuint32_t DMA13:1;
+ vuint32_t DMA12:1;
+ vuint32_t DMA11:1;
+ vuint32_t DMA10:1;
+ vuint32_t DMA9:1;
+ vuint32_t DMA8:1;
+ vuint32_t DMA7:1;
+ vuint32_t DMA6:1;
+ vuint32_t DMA5:1;
+ vuint32_t DMA4:1;
+ vuint32_t DMA3:1;
+ vuint32_t DMA2:1;
+ vuint32_t DMA1:1;
+ vuint32_t DMA0:1;
+ } B;
+ } DMAR0; /* PRECISE CHANNELS DMA REGISTER 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DMA31:1;
+ vuint32_t DMA30:1;
+ vuint32_t DMA29:1;
+ vuint32_t DMA28:1;
+ vuint32_t DMA27:1;
+ vuint32_t DMA26:1;
+ vuint32_t DMA25:1;
+ vuint32_t DMA24:1;
+ vuint32_t DMA23:1;
+ vuint32_t DMA22:1;
+ vuint32_t DMA21:1;
+ vuint32_t DMA20:1;
+ vuint32_t DMA19:1;
+ vuint32_t DMA18:1;
+ vuint32_t DMA17:1;
+ vuint32_t DMA16:1;
+ vuint32_t DMA15:1;
+ vuint32_t DMA14:1;
+ vuint32_t DMA13:1;
+ vuint32_t DMA12:1;
+ vuint32_t DMA11:1;
+ vuint32_t DMA10:1;
+ vuint32_t DMA9:1;
+ vuint32_t DMA8:1;
+ vuint32_t DMA7:1;
+ vuint32_t DMA6:1;
+ vuint32_t DMA5:1;
+ vuint32_t DMA4:1;
+ vuint32_t DMA3:1;
+ vuint32_t DMA2:1;
+ vuint32_t DMA1:1;
+ vuint32_t DMA0:1;
+ } B;
+ } DMAR1; /* EXTENDED INTERNAL CHANNELS DMA REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DMA31:1;
+ vuint32_t DMA30:1;
+ vuint32_t DMA29:1;
+ vuint32_t DMA28:1;
+ vuint32_t DMA27:1;
+ vuint32_t DMA26:1;
+ vuint32_t DMA25:1;
+ vuint32_t DMA24:1;
+ vuint32_t DMA23:1;
+ vuint32_t DMA22:1;
+ vuint32_t DMA21:1;
+ vuint32_t DMA20:1;
+ vuint32_t DMA19:1;
+ vuint32_t DMA18:1;
+ vuint32_t DMA17:1;
+ vuint32_t DMA16:1;
+ vuint32_t DMA15:1;
+ vuint32_t DMA14:1;
+ vuint32_t DMA13:1;
+ vuint32_t DMA12:1;
+ vuint32_t DMA11:1;
+ vuint32_t DMA10:1;
+ vuint32_t DMA9:1;
+ vuint32_t DMA8:1;
+ vuint32_t DMA7:1;
+ vuint32_t DMA6:1;
+ vuint32_t DMA5:1;
+ vuint32_t DMA4:1;
+ vuint32_t DMA3:1;
+ vuint32_t DMA2:1;
+ vuint32_t DMA1:1;
+ vuint32_t DMA0:1;
+ } B;
+ } DMAR2; /* EXTERNAL CHANNELS DMA REGISTER 2 */
+
+ int32_t ADC0_reserved11[4];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t THRH:10;
+ vuint32_t:6;
+ vuint32_t THRL:10;
+ } B;
+ } THRHLR[4]; /* THRESHOLD REGISTER 0-3 */
+
+
+ int32_t ADC0_reserved12[4];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t PREVAL2:2;
+ vuint32_t PREVAL1:2;
+ vuint32_t PREVAL0:2;
+ vuint32_t PRECONV:1;
+ } B;
+ } PSCR; /* PRESAMPLING CONTROL REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t PRES15:1;
+ vuint32_t PRES14:1;
+ vuint32_t PRES13:1;
+ vuint32_t PRES12:1;
+ vuint32_t PRES11:1;
+ vuint32_t PRES10:1;
+ vuint32_t PRES9:1;
+ vuint32_t PRES8:1;
+ vuint32_t PRES7:1;
+ vuint32_t PRES6:1;
+ vuint32_t PRES5:1;
+ vuint32_t PRES4:1;
+ vuint32_t PRES3:1;
+ vuint32_t PRES2:1;
+ vuint32_t PRES1:1;
+ vuint32_t PRES0:1;
+ } B;
+ } PSR0; /* PRECISE CHANNELS PRESAMPLING REGISTER 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRES31:1;
+ vuint32_t PRES30:1;
+ vuint32_t PRES29:1;
+ vuint32_t PRES28:1;
+ vuint32_t PRES27:1;
+ vuint32_t PRES26:1;
+ vuint32_t PRES25:1;
+ vuint32_t PRES24:1;
+ vuint32_t PRES23:1;
+ vuint32_t PRES22:1;
+ vuint32_t PRES21:1;
+ vuint32_t PRES20:1;
+ vuint32_t PRES19:1;
+ vuint32_t PRES18:1;
+ vuint32_t PRES17:1;
+ vuint32_t PRES16:1;
+ vuint32_t PRES15:1;
+ vuint32_t PRES14:1;
+ vuint32_t PRES13:1;
+ vuint32_t PRES12:1;
+ vuint32_t PRES11:1;
+ vuint32_t PRES10:1;
+ vuint32_t PRES9:1;
+ vuint32_t PRES8:1;
+ vuint32_t PRES7:1;
+ vuint32_t PRES6:1;
+ vuint32_t PRES5:1;
+ vuint32_t PRES4:1;
+ vuint32_t PRES3:1;
+ vuint32_t PRES2:1;
+ vuint32_t PRES1:1;
+ vuint32_t PRES0:1;
+ } B;
+ } PSR1; /* EXTENDED INTERNAL CHANNELS PRESAMPLING REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRES31:1;
+ vuint32_t PRES30:1;
+ vuint32_t PRES29:1;
+ vuint32_t PRES28:1;
+ vuint32_t PRES27:1;
+ vuint32_t PRES26:1;
+ vuint32_t PRES25:1;
+ vuint32_t PRES24:1;
+ vuint32_t PRES23:1;
+ vuint32_t PRES22:1;
+ vuint32_t PRES21:1;
+ vuint32_t PRES20:1;
+ vuint32_t PRES19:1;
+ vuint32_t PRES18:1;
+ vuint32_t PRES17:1;
+ vuint32_t PRES16:1;
+ vuint32_t PRES15:1;
+ vuint32_t PRES14:1;
+ vuint32_t PRES13:1;
+ vuint32_t PRES12:1;
+ vuint32_t PRES11:1;
+ vuint32_t PRES10:1;
+ vuint32_t PRES9:1;
+ vuint32_t PRES8:1;
+ vuint32_t PRES7:1;
+ vuint32_t PRES6:1;
+ vuint32_t PRES5:1;
+ vuint32_t PRES4:1;
+ vuint32_t PRES3:1;
+ vuint32_t PRES2:1;
+ vuint32_t PRES1:1;
+ vuint32_t PRES0:1;
+ } B;
+ } PSR2; /* EXTERNAL CHANNELS PRESAMPLING REGISTER 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC0_reserved4;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:4;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR0; /* PRECISE CHANNELS CONVERSION TIMING REGISTER 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:4;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR1; /* EXTENDED INTERNAL CHANNELS CONVERSION TIMING REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:4;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR2; /* EXTERNAL CHANNELS CONVERSION TIMING REGISTER 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC0_reserved5;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } NCMR0; /* PRECISE CHANNELS NORMAL CONVERSION MASK REGISTER 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH31:1;
+ vuint32_t CH30:1;
+ vuint32_t CH29:1;
+ vuint32_t CH28:1;
+ vuint32_t CH27:1;
+ vuint32_t CH26:1;
+ vuint32_t CH25:1;
+ vuint32_t CH24:1;
+ vuint32_t CH23:1;
+ vuint32_t CH22:1;
+ vuint32_t CH21:1;
+ vuint32_t CH20:1;
+ vuint32_t CH19:1;
+ vuint32_t CH18:1;
+ vuint32_t CH17:1;
+ vuint32_t CH16:1;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } NCMR1; /* EXTENDED INTERNAL CHANNELS NORMAL CONVERSION MASK REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH31:1;
+ vuint32_t CH30:1;
+ vuint32_t CH29:1;
+ vuint32_t CH28:1;
+ vuint32_t CH27:1;
+ vuint32_t CH26:1;
+ vuint32_t CH25:1;
+ vuint32_t CH24:1;
+ vuint32_t CH23:1;
+ vuint32_t CH22:1;
+ vuint32_t CH21:1;
+ vuint32_t CH20:1;
+ vuint32_t CH19:1;
+ vuint32_t CH18:1;
+ vuint32_t CH17:1;
+ vuint32_t CH16:1;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } NCMR2; /* EXTERNAL CHANNELS NORMAL CONVERSION MASK REGISTER 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC0_reserved6;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } JCMR0; /* PRECISE CHANNELS INJECTED CONVERSION MASK REGISTER 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH31:1;
+ vuint32_t CH30:1;
+ vuint32_t CH29:1;
+ vuint32_t CH28:1;
+ vuint32_t CH27:1;
+ vuint32_t CH26:1;
+ vuint32_t CH25:1;
+ vuint32_t CH24:1;
+ vuint32_t CH23:1;
+ vuint32_t CH22:1;
+ vuint32_t CH21:1;
+ vuint32_t CH20:1;
+ vuint32_t CH19:1;
+ vuint32_t CH18:1;
+ vuint32_t CH17:1;
+ vuint32_t CH16:1;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } JCMR1; /* EXTENDED INTERNAL CHANNELS INJECTED CONVERSION MASK REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH31:1;
+ vuint32_t CH30:1;
+ vuint32_t CH29:1;
+ vuint32_t CH28:1;
+ vuint32_t CH27:1;
+ vuint32_t CH26:1;
+ vuint32_t CH25:1;
+ vuint32_t CH24:1;
+ vuint32_t CH23:1;
+ vuint32_t CH22:1;
+ vuint32_t CH21:1;
+ vuint32_t CH20:1;
+ vuint32_t CH19:1;
+ vuint32_t CH18:1;
+ vuint32_t CH17:1;
+ vuint32_t CH16:1;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } JCMR2; /* EXTERNAL CHANNELS INJECTED CONVERSION MASK REGISTER 2 */
+
+
+ int32_t ADC0_reserved_OFFWR; /* Digital offset cancellation removed from 1.5M and removed from spec of 512K */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t DSD:8;
+ } B;
+ } DSDR; /* DECODE SIGNALS DELAY REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t PDED:8;
+ } B;
+ } PDEDR; /* POWER DOWN EXIT DELAY REGISTER */
+
+
+
+ int32_t ADC0_reserved7[13]; /* {0x100-0x0F0}/0x4 = 4 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t VALID:1;
+ vuint32_t OVERW:1;
+ vuint32_t RESULT:2;
+ vuint32_t:6;
+ vuint32_t CDATA:10;
+ } B;
+ } CDR[96]; /* CHANNEL x DATA REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t THRH:10;
+ vuint32_t:6;
+ vuint32_t THRL:10;
+ } B;
+ } THRHLR4; /* THRESHOLD REGISTER 4 */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t THRH:10;
+ vuint32_t:6;
+ vuint32_t THRL:10;
+ } B;
+ } THRHLR5; /* THRESHOLD REGISTER 5 */ /* Bolero 1.5M / ADC0 only */
+
+ int32_t ADC0_reserved8[10];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH7:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH6:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH5:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH4:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH3:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH2:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH1:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH0:3;
+ } B;
+ } CWSELR0; /* CHANNEL WATCHDOG SELECTION REGISTERS (PRECISE CHANNELS) */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH15:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH14:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH13:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH12:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH11:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH10:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH9:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH8:3;
+ } B;
+ } CWSELR1; /* CHANNEL WATCHDOG SELECTION REGISTERS (PRECISE CHANNELS) */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } CWSELR2; /* reserved (16 precise channels only) */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } CWSELR3; /* reserved (16 precise channels only) */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH39:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH38:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH37:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH36:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH35:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH34:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH33:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH32:3;
+ } B;
+ } CWSELR4; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTENDED INTERNAL CHANNELS) */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH47:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH46:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH45:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH44:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH43:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH42:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH41:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH40:3;
+ } B;
+ } CWSELR5; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTENDED INTERNAL CHANNELS) */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH55:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH54:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH53:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH52:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH51:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH50:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH49:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH48:3;
+ } B;
+ } CWSELR6; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTENDED INTERNAL CHANNELS) */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH63:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH62:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH61:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH60:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH59:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH58:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH57:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH56:3;
+ } B;
+ } CWSELR7; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTENDED INTERNAL CHANNELS) */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH71:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH70:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH69:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH68:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH67:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH66:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH65:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH64:3;
+ } B;
+ } CWSELR8; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTERNAL CHANNELS) */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH79:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH78:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH77:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH76:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH75:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH74:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH73:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH72:3;
+ } B;
+ } CWSELR9; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTERNAL CHANNELS) */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH87:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH86:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH85:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH84:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH83:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH82:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH81:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH80:3;
+ } B;
+ } CWSELR10; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTERNAL CHANNELS) */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH95:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH94:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH93:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH92:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH91:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH90:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH89:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH88:3;
+ } B;
+ } CWSELR11; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTERNAL CHANNELS) */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CWEN31:1;
+ vuint32_t CWEN30:1;
+ vuint32_t CWEN29:1;
+ vuint32_t CWEN28:1;
+ vuint32_t CWEN27:1;
+ vuint32_t CWEN26:1;
+ vuint32_t CWEN25:1;
+ vuint32_t CWEN24:1;
+ vuint32_t CWEN23:1;
+ vuint32_t CWEN22:1;
+ vuint32_t CWEN21:1;
+ vuint32_t CWEN20:1;
+ vuint32_t CWEN19:1;
+ vuint32_t CWEN18:1;
+ vuint32_t CWEN17:1;
+ vuint32_t CWEN16:1;
+ vuint32_t CWEN15:1;
+ vuint32_t CWEN14:1;
+ vuint32_t CWEN13:1;
+ vuint32_t CWEN12:1;
+ vuint32_t CWEN11:1;
+ vuint32_t CWEN10:1;
+ vuint32_t CWEN9:1;
+ vuint32_t CWEN8:1;
+ vuint32_t CWEN7:1;
+ vuint32_t CWEN6:1;
+ vuint32_t CWEN5:1;
+ vuint32_t CWEN4:1;
+ vuint32_t CWEN3:1;
+ vuint32_t CWEN2:1;
+ vuint32_t CWEN1:1;
+ vuint32_t CWEN0:1;
+ } B;
+ } CWENR[3]; /* CHANNEL WATCHDOG ENABLE REGISTERS 0-2 */
+
+ int32_t ADC0_reserved9;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t AWORR_CH31:1;
+ vuint32_t AWORR_CH30:1;
+ vuint32_t AWORR_CH29:1;
+ vuint32_t AWORR_CH28:1;
+ vuint32_t AWORR_CH27:1;
+ vuint32_t AWORR_CH26:1;
+ vuint32_t AWORR_CH25:1;
+ vuint32_t AWORR_CH24:1;
+ vuint32_t AWORR_CH23:1;
+ vuint32_t AWORR_CH22:1;
+ vuint32_t AWORR_CH21:1;
+ vuint32_t AWORR_CH20:1;
+ vuint32_t AWORR_CH19:1;
+ vuint32_t AWORR_CH18:1;
+ vuint32_t AWORR_CH17:1;
+ vuint32_t AWORR_CH16:1;
+ vuint32_t AWORR_CH15:1;
+ vuint32_t AWORR_CH14:1;
+ vuint32_t AWORR_CH13:1;
+ vuint32_t AWORR_CH12:1;
+ vuint32_t AWORR_CH11:1;
+ vuint32_t AWORR_CH10:1;
+ vuint32_t AWORR_CH9:1;
+ vuint32_t AWORR_CH8:1;
+ vuint32_t AWORR_CH7:1;
+ vuint32_t AWORR_CH6:1;
+ vuint32_t AWORR_CH5:1;
+ vuint32_t AWORR_CH4:1;
+ vuint32_t AWORR_CH3:1;
+ vuint32_t AWORR_CH2:1;
+ vuint32_t AWORR_CH1:1;
+ vuint32_t AWORR_CH0:1;
+ } B;
+ } AWORR[3]; /* ANALOG WATCHDOG OUT OF RANGE REGISTERS 0-2 */
+
+ int32_t ADC0_reserved10;
+
+ }; /* end of ADC0_tag */
+
+
+
+/****************************************************************************/
+/* MODULE : ADC1 */
+/****************************************************************************/
+ struct ADC1_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OWREN:1;
+ vuint32_t WLSIDE:1;
+ vuint32_t MODE:1;
+ vuint32_t EDGLEV:1;
+ vuint32_t TRGEN:1;
+ vuint32_t EDGE:1;
+ vuint32_t XSTRTEN:1;
+ vuint32_t NSTART:1;
+ vuint32_t:1;
+ vuint32_t JTRGEN:1;
+ vuint32_t JEDGE:1;
+ vuint32_t JSTART:1;
+ vuint32_t:2;
+ vuint32_t CTUEN:1;
+ vuint32_t:8;
+ vuint32_t ADCLKSEL:1;
+ vuint32_t ABORT_CHAIN:1;
+ vuint32_t ABORT:1;
+ vuint32_t ACKO:1;
+ vuint32_t:1; //vuint32_t OFFREFRESH:1;
+ vuint32_t:1; //vuint32_t OFFCANC:1;
+ vuint32_t:2;
+ vuint32_t PWDN:1;
+ } B;
+ } MCR; /* MAIN CONFIGURATION REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:7;
+ vuint32_t NSTART:1;
+ vuint32_t JABORT:1;
+ vuint32_t:2;
+ vuint32_t JSTART:1;
+ vuint32_t:3;
+ vuint32_t CTUSTART:1;
+ vuint32_t CHADDR:7;
+ vuint32_t:3;
+ vuint32_t ACKO:1;
+ vuint32_t:1; //vuint32_t OFFREFRESH:1;
+ vuint32_t:1; //vuint32_t OFFCANC:1;
+ vuint32_t ADCSTATUS:3;
+ } B;
+ } MSR; /* MAIN STATUS REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC1_reserved0;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC1_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t:1; //vuint32_t OFFCANCOVR:1;
+ vuint32_t:1; //vuint32_t EOFFSET:1;
+ vuint32_t EOCTU:1;
+ vuint32_t JEOC:1;
+ vuint32_t JECH:1;
+ vuint32_t EOC:1;
+ vuint32_t ECH:1;
+ } B;
+ } ISR; /* INTERRUPT STATUS REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t EOC_CH15:1;
+ vuint32_t EOC_CH14:1;
+ vuint32_t EOC_CH13:1;
+ vuint32_t EOC_CH12:1;
+ vuint32_t EOC_CH11:1;
+ vuint32_t EOC_CH10:1;
+ vuint32_t EOC_CH9:1;
+ vuint32_t EOC_CH8:1;
+ vuint32_t EOC_CH7:1;
+ vuint32_t EOC_CH6:1;
+ vuint32_t EOC_CH5:1;
+ vuint32_t EOC_CH4:1;
+ vuint32_t EOC_CH3:1;
+ vuint32_t EOC_CH2:1;
+ vuint32_t EOC_CH1:1;
+ vuint32_t EOC_CH0:1;
+ } B;
+ } CE0CFR0; /* PRECISE CHANNELS PENDING REGISTERS */
+
+ int32_t ADC1_reserved11[2];
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t:1; //vuint32_t MSKOFFCANCOVR:1;
+ vuint32_t:1; //vuint32_t MSKEOFFSET:1;
+ vuint32_t MSKEOCTU:1;
+ vuint32_t MSKJEOC:1;
+ vuint32_t MSKJECH:1;
+ vuint32_t MSKEOC:1;
+ vuint32_t MSKECH:1;
+ } B;
+ } IMR; /* INTERRUPT MASK REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CIM15:1;
+ vuint32_t CIM14:1;
+ vuint32_t CIM13:1;
+ vuint32_t CIM12:1;
+ vuint32_t CIM11:1;
+ vuint32_t CIM10:1;
+ vuint32_t CIM9:1;
+ vuint32_t CIM8:1;
+ vuint32_t CIM7:1;
+ vuint32_t CIM6:1;
+ vuint32_t CIM5:1;
+ vuint32_t CIM4:1;
+ vuint32_t CIM3:1;
+ vuint32_t CIM2:1;
+ vuint32_t CIM1:1;
+ vuint32_t CIM0:1;
+ } B;
+ } CIMR0; /* PRECISE CHANNELS INTERRUPT MASK 0 */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CIM63:1;
+ vuint32_t CIM62:1;
+ vuint32_t CIM61:1;
+ vuint32_t CIM60:1;
+ vuint32_t CIM59:1;
+ vuint32_t CIM58:1;
+ vuint32_t CIM57:1;
+ vuint32_t CIM56:1;
+ vuint32_t CIM55:1;
+ vuint32_t CIM54:1;
+ vuint32_t CIM53:1;
+ vuint32_t CIM52:1;
+ vuint32_t CIM51:1;
+ vuint32_t CIM50:1;
+ vuint32_t CIM49:1;
+ vuint32_t CIM48:1;
+ vuint32_t CIM47:1;
+ vuint32_t CIM46:1;
+ vuint32_t CIM45:1;
+ vuint32_t CIM44:1;
+ vuint32_t CIM43:1;
+ vuint32_t CIM42:1;
+ vuint32_t CIM41:1;
+ vuint32_t CIM40:1;
+ vuint32_t CIM39:1;
+ vuint32_t CIM38:1;
+ vuint32_t CIM37:1;
+ vuint32_t CIM36:1;
+ vuint32_t CIM35:1;
+ vuint32_t CIM34:1;
+ vuint32_t CIM33:1;
+ vuint32_t CIM32:1;
+ } B;
+ } CIMR1; /* EXTENDED CHANNELS INTERRUPT MASK 1 */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CIM95:1;
+ vuint32_t CIM94:1;
+ vuint32_t CIM93:1;
+ vuint32_t CIM92:1;
+ vuint32_t CIM91:1;
+ vuint32_t CIM90:1;
+ vuint32_t CIM89:1;
+ vuint32_t CIM88:1;
+ vuint32_t CIM87:1;
+ vuint32_t CIM86:1;
+ vuint32_t CIM85:1;
+ vuint32_t CIM84:1;
+ vuint32_t CIM83:1;
+ vuint32_t CIM82:1;
+ vuint32_t CIM81:1;
+ vuint32_t CIM80:1;
+ vuint32_t CIM79:1;
+ vuint32_t CIM78:1;
+ vuint32_t CIM77:1;
+ vuint32_t CIM76:1;
+ vuint32_t CIM75:1;
+ vuint32_t CIM74:1;
+ vuint32_t CIM73:1;
+ vuint32_t CIM72:1;
+ vuint32_t CIM71:1;
+ vuint32_t CIM70:1;
+ vuint32_t CIM69:1;
+ vuint32_t CIM68:1;
+ vuint32_t CIM67:1;
+ vuint32_t CIM66:1;
+ vuint32_t CIM65:1;
+ vuint32_t CIM64:1;
+ } B;
+ } CIMR2; /* EXTERNAL CHANNELS INTERRUPT MASK 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t WDG5H:1; // non validi
+ vuint32_t WDG5L:1; // non validi
+ vuint32_t WDG4H:1; // non validi
+ vuint32_t WDG4L:1; // non validi
+ vuint32_t WDG3H:1; // validi
+ vuint32_t WDG3L:1; // validi
+ vuint32_t WDG2H:1; // validi
+ vuint32_t WDG2L:1; // validi
+ vuint32_t WDG1H:1; // validi
+ vuint32_t WDG1L:1; // validi
+ vuint32_t WDG0H:1; // validi
+ vuint32_t WDG0L:1; // validi
+ } B;
+ } WTISR; /* WATCHDOG THRESHOLD INTERRUPT STATUS REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t MSKWDG5H:1; // non validi
+ vuint32_t MSKWDG5L:1; // non validi
+ vuint32_t MSKWDG4H:1; // non validi
+ vuint32_t MSKWDG4L:1; // non validi
+ vuint32_t MSKWDG3H:1; // validi
+ vuint32_t MSKWDG2H:1; // validi
+ vuint32_t MSKWDG1H:1; // validi
+ vuint32_t MSKWDG0H:1; // validi
+ vuint32_t MSKWDG3L:1; // validi
+ vuint32_t MSKWDG2L:1; // validi
+ vuint32_t MSKWDG1L:1; // validi
+ vuint32_t MSKWDG0L:1; // validi
+ } B;
+ } WTIMR; /* WATCHDOG THRESHOLD INTERRUPT MASK REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC1_reserved2;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC1_reserved3;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t DCLR:1;
+ vuint32_t DMAEN:1;
+ } B;
+ } DMAE; /* DMA ENABLE REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DMA15:1;
+ vuint32_t DMA14:1;
+ vuint32_t DMA13:1;
+ vuint32_t DMA12:1;
+ vuint32_t DMA11:1;
+ vuint32_t DMA10:1;
+ vuint32_t DMA9:1;
+ vuint32_t DMA8:1;
+ vuint32_t DMA7:1;
+ vuint32_t DMA6:1;
+ vuint32_t DMA5:1;
+ vuint32_t DMA4:1;
+ vuint32_t DMA3:1;
+ vuint32_t DMA2:1;
+ vuint32_t DMA1:1;
+ vuint32_t DMA0:1;
+ } B;
+ } DMAR0; /* PRECISE CHANNELS DMA REGISTER 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DMA63:1;
+ vuint32_t DMA62:1;
+ vuint32_t DMA61:1;
+ vuint32_t DMA60:1;
+ vuint32_t DMA59:1;
+ vuint32_t DMA58:1;
+ vuint32_t DMA57:1;
+ vuint32_t DMA56:1;
+ vuint32_t DMA55:1;
+ vuint32_t DMA54:1;
+ vuint32_t DMA53:1;
+ vuint32_t DMA52:1;
+ vuint32_t DMA51:1;
+ vuint32_t DMA50:1;
+ vuint32_t DMA49:1;
+ vuint32_t DMA48:1;
+ vuint32_t DMA47:1;
+ vuint32_t DMA46:1;
+ vuint32_t DMA45:1;
+ vuint32_t DMA44:1;
+ vuint32_t DMA43:1;
+ vuint32_t DMA42:1;
+ vuint32_t DMA41:1;
+ vuint32_t DMA40:1;
+ vuint32_t DMA39:1;
+ vuint32_t DMA38:1;
+ vuint32_t DMA37:1;
+ vuint32_t DMA36:1;
+ vuint32_t DMA35:1;
+ vuint32_t DMA34:1;
+ vuint32_t DMA33:1;
+ vuint32_t DMA32:1;
+ } B;
+ } DMAR1; /* EXTENDED INTERNAL CHANNELS DMA REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DMA95:1;
+ vuint32_t DMA94:1;
+ vuint32_t DMA93:1;
+ vuint32_t DMA92:1;
+ vuint32_t DMA91:1;
+ vuint32_t DMA90:1;
+ vuint32_t DMA89:1;
+ vuint32_t DMA88:1;
+ vuint32_t DMA87:1;
+ vuint32_t DMA86:1;
+ vuint32_t DMA85:1;
+ vuint32_t DMA84:1;
+ vuint32_t DMA83:1;
+ vuint32_t DMA82:1;
+ vuint32_t DMA81:1;
+ vuint32_t DMA80:1;
+ vuint32_t DMA79:1;
+ vuint32_t DMA78:1;
+ vuint32_t DMA77:1;
+ vuint32_t DMA76:1;
+ vuint32_t DMA75:1;
+ vuint32_t DMA74:1;
+ vuint32_t DMA73:1;
+ vuint32_t DMA72:1;
+ vuint32_t DMA71:1;
+ vuint32_t DMA70:1;
+ vuint32_t DMA69:1;
+ vuint32_t DMA68:1;
+ vuint32_t DMA67:1;
+ vuint32_t DMA66:1;
+ vuint32_t DMA65:1;
+ vuint32_t DMA64:1;
+ } B;
+ } DMAR2; /* EXTERNAL CHANNELS DMA REGISTER 2 */
+
+ int32_t ADC1_reserved13[4];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12;
+ vuint32_t:4;
+ vuint32_t THRL:12;
+ } B;
+ } THRHLR[3]; /* THRESHOLD REGISTER 0-2 */
+
+ int32_t ADC1_reserved14[5];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t PREVAL2:2;
+ vuint32_t PREVAL1:2;
+ vuint32_t PREVAL0:2;
+ vuint32_t PRECONV:1;
+ } B;
+ } PSCR; /* PRESAMPLING CONTROL REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t PRES15:1;
+ vuint32_t PRES14:1;
+ vuint32_t PRES13:1;
+ vuint32_t PRES12:1;
+ vuint32_t PRES11:1;
+ vuint32_t PRES10:1;
+ vuint32_t PRES9:1;
+ vuint32_t PRES8:1;
+ vuint32_t PRES7:1;
+ vuint32_t PRES6:1;
+ vuint32_t PRES5:1;
+ vuint32_t PRES4:1;
+ vuint32_t PRES3:1;
+ vuint32_t PRES2:1;
+ vuint32_t PRES1:1;
+ vuint32_t PRES0:1;
+ } B;
+ } PSR0; /* PRECISE CHANNELS PRESAMPLING REGISTER 0 */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRES63:1;
+ vuint32_t PRES62:1;
+ vuint32_t PRES61:1;
+ vuint32_t PRES60:1;
+ vuint32_t PRES59:1;
+ vuint32_t PRES58:1;
+ vuint32_t PRES57:1;
+ vuint32_t PRES56:1;
+ vuint32_t PRES55:1;
+ vuint32_t PRES54:1;
+ vuint32_t PRES53:1;
+ vuint32_t PRES52:1;
+ vuint32_t PRES51:1;
+ vuint32_t PRES50:1;
+ vuint32_t PRES49:1;
+ vuint32_t PRES48:1;
+ vuint32_t PRES47:1;
+ vuint32_t PRES46:1;
+ vuint32_t PRES45:1;
+ vuint32_t PRES44:1;
+ vuint32_t PRES43:1;
+ vuint32_t PRES42:1;
+ vuint32_t PRES41:1;
+ vuint32_t PRES40:1;
+ vuint32_t PRES39:1;
+ vuint32_t PRES38:1;
+ vuint32_t PRES37:1;
+ vuint32_t PRES36:1;
+ vuint32_t PRES35:1;
+ vuint32_t PRES34:1;
+ vuint32_t PRES33:1;
+ vuint32_t PRES32:1;
+ } B;
+ } PSR1; /* EXTENDED CHANNELS PRESAMPLING REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRES95:1;
+ vuint32_t PRES94:1;
+ vuint32_t PRES93:1;
+ vuint32_t PRES92:1;
+ vuint32_t PRES91:1;
+ vuint32_t PRES90:1;
+ vuint32_t PRES89:1;
+ vuint32_t PRES88:1;
+ vuint32_t PRES87:1;
+ vuint32_t PRES86:1;
+ vuint32_t PRES85:1;
+ vuint32_t PRES84:1;
+ vuint32_t PRES83:1;
+ vuint32_t PRES82:1;
+ vuint32_t PRES81:1;
+ vuint32_t PRES80:1;
+ vuint32_t PRES79:1;
+ vuint32_t PRES78:1;
+ vuint32_t PRES77:1;
+ vuint32_t PRES76:1;
+ vuint32_t PRES75:1;
+ vuint32_t PRES74:1;
+ vuint32_t PRES73:1;
+ vuint32_t PRES72:1;
+ vuint32_t PRES71:1;
+ vuint32_t PRES70:1;
+ vuint32_t PRES69:1;
+ vuint32_t PRES68:1;
+ vuint32_t PRES67:1;
+ vuint32_t PRES66:1;
+ vuint32_t PRES65:1;
+ vuint32_t PRES64:1;
+ } B;
+ } PSR2; /* EXTERNAL CHANNELS PRESAMPLING REGISTER 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC1_reserved4;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:4;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR0; /* PRECISE CHANNELS CONVERSION TIMING REGISTER 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:4;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR1; /* EXTENDED CHANNELS CONVERSION TIMING REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:4;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR2; /* EXTERNAL CHANNELS CONVERSION TIMING REGISTER 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC1_reserved5;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } NCMR0; /* PRECISE CHANNELS NORMAL CONVERSION MASK REGISTER 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH63:1;
+ vuint32_t CH62:1;
+ vuint32_t CH61:1;
+ vuint32_t CH60:1;
+ vuint32_t CH59:1;
+ vuint32_t CH58:1;
+ vuint32_t CH57:1;
+ vuint32_t CH56:1;
+ vuint32_t CH55:1;
+ vuint32_t CH54:1;
+ vuint32_t CH53:1;
+ vuint32_t CH52:1;
+ vuint32_t CH51:1;
+ vuint32_t CH50:1;
+ vuint32_t CH49:1;
+ vuint32_t CH48:1;
+ vuint32_t CH47:1;
+ vuint32_t CH46:1;
+ vuint32_t CH45:1;
+ vuint32_t CH44:1;
+ vuint32_t CH43:1;
+ vuint32_t CH42:1;
+ vuint32_t CH41:1;
+ vuint32_t CH40:1;
+ vuint32_t CH39:1;
+ vuint32_t CH38:1;
+ vuint32_t CH37:1;
+ vuint32_t CH36:1;
+ vuint32_t CH35:1;
+ vuint32_t CH34:1;
+ vuint32_t CH33:1;
+ vuint32_t CH32:1;
+ } B;
+ } NCMR1; /* EXTENDED CHANNELS NORMAL CONVERSION MASK REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH95:1;
+ vuint32_t CH94:1;
+ vuint32_t CH93:1;
+ vuint32_t CH92:1;
+ vuint32_t CH91:1;
+ vuint32_t CH90:1;
+ vuint32_t CH89:1;
+ vuint32_t CH88:1;
+ vuint32_t CH87:1;
+ vuint32_t CH86:1;
+ vuint32_t CH85:1;
+ vuint32_t CH84:1;
+ vuint32_t CH83:1;
+ vuint32_t CH82:1;
+ vuint32_t CH81:1;
+ vuint32_t CH80:1;
+ vuint32_t CH79:1;
+ vuint32_t CH78:1;
+ vuint32_t CH77:1;
+ vuint32_t CH76:1;
+ vuint32_t CH75:1;
+ vuint32_t CH74:1;
+ vuint32_t CH73:1;
+ vuint32_t CH72:1;
+ vuint32_t CH71:1;
+ vuint32_t CH70:1;
+ vuint32_t CH69:1;
+ vuint32_t CH68:1;
+ vuint32_t CH67:1;
+ vuint32_t CH66:1;
+ vuint32_t CH65:1;
+ vuint32_t CH64:1;
+ } B;
+ } NCMR2; /* EXTERNAL CHANNELS NORMAL CONVERSION MASK REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC1_reserved6;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } JCMR0; /* PRECISE CHANNELS INJECTED CONVERSION MASK REGISTER 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH63:1;
+ vuint32_t CH62:1;
+ vuint32_t CH61:1;
+ vuint32_t CH60:1;
+ vuint32_t CH59:1;
+ vuint32_t CH58:1;
+ vuint32_t CH57:1;
+ vuint32_t CH56:1;
+ vuint32_t CH55:1;
+ vuint32_t CH54:1;
+ vuint32_t CH53:1;
+ vuint32_t CH52:1;
+ vuint32_t CH51:1;
+ vuint32_t CH50:1;
+ vuint32_t CH49:1;
+ vuint32_t CH48:1;
+ vuint32_t CH47:1;
+ vuint32_t CH46:1;
+ vuint32_t CH45:1;
+ vuint32_t CH44:1;
+ vuint32_t CH43:1;
+ vuint32_t CH42:1;
+ vuint32_t CH41:1;
+ vuint32_t CH40:1;
+ vuint32_t CH39:1;
+ vuint32_t CH38:1;
+ vuint32_t CH37:1;
+ vuint32_t CH36:1;
+ vuint32_t CH35:1;
+ vuint32_t CH34:1;
+ vuint32_t CH33:1;
+ vuint32_t CH32:1;
+ } B;
+ } JCMR1; /* EXTENDED CHANNELS INJECTED CONVERSION MASK REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH95:1;
+ vuint32_t CH94:1;
+ vuint32_t CH93:1;
+ vuint32_t CH92:1;
+ vuint32_t CH91:1;
+ vuint32_t CH90:1;
+ vuint32_t CH89:1;
+ vuint32_t CH88:1;
+ vuint32_t CH87:1;
+ vuint32_t CH86:1;
+ vuint32_t CH85:1;
+ vuint32_t CH84:1;
+ vuint32_t CH83:1;
+ vuint32_t CH82:1;
+ vuint32_t CH81:1;
+ vuint32_t CH80:1;
+ vuint32_t CH79:1;
+ vuint32_t CH78:1;
+ vuint32_t CH77:1;
+ vuint32_t CH76:1;
+ vuint32_t CH75:1;
+ vuint32_t CH74:1;
+ vuint32_t CH73:1;
+ vuint32_t CH72:1;
+ vuint32_t CH71:1;
+ vuint32_t CH70:1;
+ vuint32_t CH69:1;
+ vuint32_t CH68:1;
+ vuint32_t CH67:1;
+ vuint32_t CH66:1;
+ vuint32_t CH65:1;
+ vuint32_t CH64:1;
+ } B;
+ } JCMR2; /* EXTERNAL CHANNELS INJECTED CONVERSION MASK REGISTER 2 */
+
+ int32_t ADC1_reserved18[1];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t DSD:8;
+ } B;
+ } DSDR; /* DECODE SIGNALS DELAY REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t PDED:8;
+ } B;
+ } PDEDR; /* POWER DOWN EXIT DELAY REGISTER */
+
+
+ int32_t ADC1_reserved7[13]; /* {0x100-0x0F0}/0x4 = 4 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t VALID:1;
+ vuint32_t OVERW:1;
+ vuint32_t RESULT:2;
+ vuint32_t:4;
+ vuint32_t CDATA:12;
+ } B;
+ } CDR[95]; /* CHANNEL x DATA REGISTER */
+
+
+
+ int32_t ADC1_reserved8[13];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH7:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH6:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH5:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH4:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH3:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH2:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH1:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH0:3;
+ } B;
+ } CWSELR0; /* CHANNEL WATCHDOG SELECTION REGISTERS (PRECISE CHANNELS) */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH15:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH14:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH13:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH12:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH11:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH10:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH9:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH8:3;
+ } B;
+ } CWSELR1; /* CHANNEL WATCHDOG SELECTION REGISTERS (PRECISE CHANNELS) */
+
+ int32_t ADC1_reserved19[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH39:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH38:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH37:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH36:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH35:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH34:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH33:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH32:3;
+ } B;
+ } CWSELR4; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTENDED CHANNELS) */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH47:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH46:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH45:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH44:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH43:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH42:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH41:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH40:3;
+ } B;
+ } CWSELR5; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTENDED CHANNELS) */
+
+ int32_t ADC1_reserved20[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH71:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH70:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH69:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH68:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH67:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH66:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH65:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH64:3;
+ } B;
+ } CWSELR8; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTERNAL CHANNELS) */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH79:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH78:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH77:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH76:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH75:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH74:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH73:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH72:3;
+ } B;
+ } CWSELR9; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTERNAL CHANNELS) */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH87:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH86:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH85:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH84:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH83:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH82:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH81:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH80:3;
+ } B;
+ } CWSELR10; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTERNAL CHANNELS) */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH95:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH94:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH93:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH92:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH91:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH90:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH89:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH88:3;
+ } B;
+ } CWSELR11; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTERNAL CHANNELS) */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CWEN31:1;
+ vuint32_t CWEN30:1;
+ vuint32_t CWEN29:1;
+ vuint32_t CWEN28:1;
+ vuint32_t CWEN27:1;
+ vuint32_t CWEN26:1;
+ vuint32_t CWEN25:1;
+ vuint32_t CWEN24:1;
+ vuint32_t CWEN23:1;
+ vuint32_t CWEN22:1;
+ vuint32_t CWEN21:1;
+ vuint32_t CWEN20:1;
+ vuint32_t CWEN19:1;
+ vuint32_t CWEN18:1;
+ vuint32_t CWEN17:1;
+ vuint32_t CWEN16:1;
+ vuint32_t CWEN15:1;
+ vuint32_t CWEN14:1;
+ vuint32_t CWEN13:1;
+ vuint32_t CWEN12:1;
+ vuint32_t CWEN11:1;
+ vuint32_t CWEN10:1;
+ vuint32_t CWEN9:1;
+ vuint32_t CWEN8:1;
+ vuint32_t CWEN7:1;
+ vuint32_t CWEN6:1;
+ vuint32_t CWEN5:1;
+ vuint32_t CWEN4:1;
+ vuint32_t CWEN3:1;
+ vuint32_t CWEN2:1;
+ vuint32_t CWEN1:1;
+ vuint32_t CWEN0:1;
+ } B;
+ } CWENR[3]; /* CHANNEL WATCHDOG ENABLE REGISTERS 0-2 */
+
+ int32_t ADC1_reserved9[1];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t AWORR_CH31:1;
+ vuint32_t AWORR_CH30:1;
+ vuint32_t AWORR_CH29:1;
+ vuint32_t AWORR_CH28:1;
+ vuint32_t AWORR_CH27:1;
+ vuint32_t AWORR_CH26:1;
+ vuint32_t AWORR_CH25:1;
+ vuint32_t AWORR_CH24:1;
+ vuint32_t AWORR_CH23:1;
+ vuint32_t AWORR_CH22:1;
+ vuint32_t AWORR_CH21:1;
+ vuint32_t AWORR_CH20:1;
+ vuint32_t AWORR_CH19:1;
+ vuint32_t AWORR_CH18:1;
+ vuint32_t AWORR_CH17:1;
+ vuint32_t AWORR_CH16:1;
+ vuint32_t AWORR_CH15:1;
+ vuint32_t AWORR_CH14:1;
+ vuint32_t AWORR_CH13:1;
+ vuint32_t AWORR_CH12:1;
+ vuint32_t AWORR_CH11:1;
+ vuint32_t AWORR_CH10:1;
+ vuint32_t AWORR_CH9:1;
+ vuint32_t AWORR_CH8:1;
+ vuint32_t AWORR_CH7:1;
+ vuint32_t AWORR_CH6:1;
+ vuint32_t AWORR_CH5:1;
+ vuint32_t AWORR_CH4:1;
+ vuint32_t AWORR_CH3:1;
+ vuint32_t AWORR_CH2:1;
+ vuint32_t AWORR_CH1:1;
+ vuint32_t AWORR_CH0:1;
+ } B;
+ } AWORR[3]; /* ANALOG WATCHDOG OUT OF RANGE REGISTERS */
+
+ }; /* end of ADC1_tag */
+
+
+
+/****************************************************************************/
+/* MODULE : CANSP */
+/****************************************************************************/
+ struct CANSP_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RX_COMPLETE:1;
+ vuint32_t BUSY:1;
+ vuint32_t ACTIVE_CK:1;
+ vuint32_t:3;
+ vuint32_t MODE:1;
+ vuint32_t CAN_RX_SEL:3;
+ vuint32_t BRP:5;
+ vuint32_t CAN_SMPLR_EN:1;
+ } B;
+ } CR; /* CANSP Control Register */
+
+ union {
+ vuint32_t R;
+ } SR[12]; /* CANSP Sample Register 0 to 11 */
+
+ }; /* end of CANSP_tag */
+/****************************************************************************/
+/* MODULE : MCM */
+/****************************************************************************/
+ struct ECSM_tag {
+
+ union {
+ vuint16_t R;
+ } PCT; /* MCM Processor Core Type Register */
+
+ union {
+ vuint16_t R;
+ } REV; /* MCM Revision Register */
+
+ int32_t MCM_reserved;
+
+ union {
+ vuint32_t R;
+ } MC; /* MCM Configuration Register */
+
+ int8_t MCM_reserved1[3];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t POR:1;
+ vuint8_t DIR:1;
+ vuint8_t:6;
+ } B;
+ } MRSR; /* MCM Miscellaneous Reset Status Register */
+
+ int8_t MCM_reserved2[3];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t ENBWCR:1;
+ vuint8_t:3;
+ vuint8_t PRILVL:4;
+ } B;
+ } MWCR; /* MCM Miscellaneous Wakeup Control Register */
+
+ int32_t MCM_reserved3[2];
+ int8_t MCM_reserved4[3];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t FB0AI:1;
+ vuint8_t FB0SI:1;
+ vuint8_t FB1AI:1;
+ vuint8_t FB1SI:1;
+ vuint8_t:4;
+ } B;
+ } MIR; /* MCM Miscellaneous Interrupt Register */
+
+ int32_t MCM_reserved5;
+
+ union {
+ vuint32_t R;
+ } MUDCR; /* MCM Miscellaneous User-Defined Control Register */
+
+ int32_t MCM_reserved6[6]; /* (0x040- 0x028)/4 = 0x06 */
+ int8_t MCM_reserved7[3];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:2;
+ vuint8_t ER1BR:1;
+ vuint8_t EF1BR:1;
+ vuint8_t:2;
+ vuint8_t ERNCR:1;
+ vuint8_t EFNCR:1;
+ } B;
+ } ECR; /* MCM ECC Configuration Register */
+
+ int8_t MCM_reserved8[3];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:2;
+ vuint8_t R1BC:1;
+ vuint8_t F1BC:1;
+ vuint8_t:2;
+ vuint8_t RNCE:1;
+ vuint8_t FNCE:1;
+ } B;
+ } ESR; /* MCM ECC Status Register */
+
+ int16_t MCM_reserved9;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t FRC1BI:1;
+ vuint16_t FR11BI:1;
+ vuint16_t:2;
+ vuint16_t FRCNCI:1;
+ vuint16_t FR1NCI:1;
+ vuint16_t:1;
+ vuint16_t ERRBIT:7;
+ } B;
+ } EEGR; /* MCM ECC Error Generation Register */
+
+ int32_t MCM_reserved10;
+
+ union {
+ vuint32_t R;
+ } FEAR; /* MCM Flash ECC Address Register */
+
+ int16_t MCM_reserved11;
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t FEMR:4;
+ } B;
+ } FEMR; /* MCM Flash ECC Master Number Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t WRITE:1;
+ vuint8_t SIZE:3;
+ vuint8_t PROTECTION:4;
+ } B;
+ } FEAT; /* MCM Flash ECC Attributes Register */
+
+ int32_t MCM_reserved12;
+
+ union {
+ vuint32_t R;
+ } FEDR; /* MCM Flash ECC Data Register */
+
+ union {
+ vuint32_t R;
+ } REAR; /* MCM RAM ECC Address Register */
+
+ int8_t MCM_reserved13;
+
+ union {
+ vuint8_t R;
+ } RESR; /* MCM RAM ECC Address Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t REMR:4;
+ } B;
+ } REMR; /* MCM RAM ECC Master Number Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t WRITE:1;
+ vuint8_t SIZE:3;
+ vuint8_t PROTECTION:4;
+ } B;
+ } REAT; /* MCM RAM ECC Attributes Register */
+
+ int32_t MCM_reserved14;
+
+ union {
+ vuint32_t R;
+ } REDR; /* MCM RAM ECC Data Register */
+
+ }; /* end of MCM_tag */
+/****************************************************************************/
+/* MODULE : RTC */
+/****************************************************************************/
+ struct RTC_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SUPV:1;
+ vuint32_t:31;
+ } B;
+ } RTCSUPV; /* RTC Supervisor Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CNTEN:1;
+ vuint32_t RTCIE:1;
+ vuint32_t FRZEN:1;
+ vuint32_t ROVREN:1;
+ vuint32_t RTCVAL:12;
+ vuint32_t APIEN:1;
+ vuint32_t APIE:1;
+ vuint32_t CLKSEL:2;
+ vuint32_t DIV512EN:1;
+ vuint32_t DIV32EN:1;
+ vuint32_t APIVAL:10;
+ } B;
+ } RTCC; /* RTC Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:2;
+ vuint32_t RTCF:1;
+ vuint32_t:15;
+ vuint32_t APIF:1;
+ vuint32_t:2;
+ vuint32_t ROVRF:1;
+ vuint32_t:10;
+ } B;
+ } RTCS; /* RTC Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t RTCCNT:32;
+ } B;
+ } RTCCNT; /* RTC Counter Register */
+
+ }; /* end of RTC_tag */
+/****************************************************************************/
+/* MODULE : SIU */
+/****************************************************************************/
+ struct SIU_tag {
+
+ int32_t SIU_reserved0;
+
+ union { /* MCU ID Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t PARTNUM:16;
+ vuint32_t CSP:1;
+ vuint32_t PKG:5;
+ vuint32_t:2;
+ vuint32_t MAJOR_MASK:4;
+ vuint32_t MINOR_MASK:4;
+ } B;
+ } MIDR;
+
+ union { /* MCU ID Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t SF:1;
+ vuint32_t FLASH_SIZE_1:4;
+ vuint32_t FLASH_SIZE_2:4;
+ vuint32_t:7;
+ vuint32_t PARTNUM:8;
+ vuint32_t:3;
+ vuint32_t EE:1;
+ vuint32_t:4;
+ } B;
+ } MIDR2;
+
+ int32_t SIU_reserved1[2];
+
+ union { /* Interrupt Status Flag Register */
+ vuint32_t R;
+ struct {
+ vuint32_t EIF31:1;
+ vuint32_t EIF30:1;
+ vuint32_t EIF29:1;
+ vuint32_t EIF28:1;
+ vuint32_t EIF27:1;
+ vuint32_t EIF26:1;
+ vuint32_t EIF25:1;
+ vuint32_t EIF24:1;
+ vuint32_t EIF23:1;
+ vuint32_t EIF22:1;
+ vuint32_t EIF21:1;
+ vuint32_t EIF20:1;
+ vuint32_t EIF19:1;
+ vuint32_t EIF18:1;
+ vuint32_t EIF17:1;
+ vuint32_t EIF16:1;
+ vuint32_t EIF15:1;
+ vuint32_t EIF14:1;
+ vuint32_t EIF13:1;
+ vuint32_t EIF12:1;
+ vuint32_t EIF11:1;
+ vuint32_t EIF10:1;
+ vuint32_t EIF9:1;
+ vuint32_t EIF8:1;
+ vuint32_t EIF7:1;
+ vuint32_t EIF6:1;
+ vuint32_t EIF5:1;
+ vuint32_t EIF4:1;
+ vuint32_t EIF3:1;
+ vuint32_t EIF2:1;
+ vuint32_t EIF1:1;
+ vuint32_t EIF0:1;
+ } B;
+ } ISR;
+
+ union { /* Interrupt Request Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t EIRE31:1;
+ vuint32_t EIRE30:1;
+ vuint32_t EIRE29:1;
+ vuint32_t EIRE28:1;
+ vuint32_t EIRE27:1;
+ vuint32_t EIRE26:1;
+ vuint32_t EIRE25:1;
+ vuint32_t EIRE24:1;
+ vuint32_t EIRE23:1;
+ vuint32_t EIRE22:1;
+ vuint32_t EIRE21:1;
+ vuint32_t EIRE20:1;
+ vuint32_t EIRE19:1;
+ vuint32_t EIRE18:1;
+ vuint32_t EIRE17:1;
+ vuint32_t EIRE16:1;
+ vuint32_t EIRE15:1;
+ vuint32_t EIRE14:1;
+ vuint32_t EIRE13:1;
+ vuint32_t EIRE12:1;
+ vuint32_t EIRE11:1;
+ vuint32_t EIRE10:1;
+ vuint32_t EIRE9:1;
+ vuint32_t EIRE8:1;
+ vuint32_t EIRE7:1;
+ vuint32_t EIRE6:1;
+ vuint32_t EIRE5:1;
+ vuint32_t EIRE4:1;
+ vuint32_t EIRE3:1;
+ vuint32_t EIRE2:1;
+ vuint32_t EIRE1:1;
+ vuint32_t EIRE0:1;
+ } B;
+ } IRER;
+
+ int32_t SIU_reserved2[3];
+
+ union { /* Interrupt Rising-Edge Event Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t IREE31:1;
+ vuint32_t IREE30:1;
+ vuint32_t IREE29:1;
+ vuint32_t IREE28:1;
+ vuint32_t IREE27:1;
+ vuint32_t IREE26:1;
+ vuint32_t IREE25:1;
+ vuint32_t IREE24:1;
+ vuint32_t IREE23:1;
+ vuint32_t IREE22:1;
+ vuint32_t IREE21:1;
+ vuint32_t IREE20:1;
+ vuint32_t IREE19:1;
+ vuint32_t IREE18:1;
+ vuint32_t IREE17:1;
+ vuint32_t IREE16:1;
+ vuint32_t IREE15:1;
+ vuint32_t IREE14:1;
+ vuint32_t IREE13:1;
+ vuint32_t IREE12:1;
+ vuint32_t IREE11:1;
+ vuint32_t IREE10:1;
+ vuint32_t IREE9:1;
+ vuint32_t IREE8:1;
+ vuint32_t IREE7:1;
+ vuint32_t IREE6:1;
+ vuint32_t IREE5:1;
+ vuint32_t IREE4:1;
+ vuint32_t IREE3:1;
+ vuint32_t IREE2:1;
+ vuint32_t IREE1:1;
+ vuint32_t IREE0:1;
+ } B;
+ } IREER;
+
+ union { /* Interrupt Falling-Edge Event Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t IFEE31:1;
+ vuint32_t IFEE30:1;
+ vuint32_t IFEE29:1;
+ vuint32_t IFEE28:1;
+ vuint32_t IFEE27:1;
+ vuint32_t IFEE26:1;
+ vuint32_t IFEE25:1;
+ vuint32_t IFEE24:1;
+ vuint32_t IFEE23:1;
+ vuint32_t IFEE22:1;
+ vuint32_t IFEE21:1;
+ vuint32_t IFEE20:1;
+ vuint32_t IFEE19:1;
+ vuint32_t IFEE18:1;
+ vuint32_t IFEE17:1;
+ vuint32_t IFEE16:1;
+ vuint32_t IFEE15:1;
+ vuint32_t IFEE14:1;
+ vuint32_t IFEE13:1;
+ vuint32_t IFEE12:1;
+ vuint32_t IFEE11:1;
+ vuint32_t IFEE10:1;
+ vuint32_t IFEE9:1;
+ vuint32_t IFEE8:1;
+ vuint32_t IFEE7:1;
+ vuint32_t IFEE6:1;
+ vuint32_t IFEE5:1;
+ vuint32_t IFEE4:1;
+ vuint32_t IFEE3:1;
+ vuint32_t IFEE2:1;
+ vuint32_t IFEE1:1;
+ vuint32_t IFEE0:1;
+ } B;
+ } IFEER;
+
+ union { /* Interrupt Filter Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t IFE31:1;
+ vuint32_t IFE30:1;
+ vuint32_t IFE29:1;
+ vuint32_t IFE28:1;
+ vuint32_t IFE27:1;
+ vuint32_t IFE26:1;
+ vuint32_t IFE25:1;
+ vuint32_t IFE24:1;
+ vuint32_t IFE23:1;
+ vuint32_t IFE22:1;
+ vuint32_t IFE21:1;
+ vuint32_t IFE20:1;
+ vuint32_t IFE19:1;
+ vuint32_t IFE18:1;
+ vuint32_t IFE17:1;
+ vuint32_t IFE16:1;
+ vuint32_t IFE15:1;
+ vuint32_t IFE14:1;
+ vuint32_t IFE13:1;
+ vuint32_t IFE12:1;
+ vuint32_t IFE11:1;
+ vuint32_t IFE10:1;
+ vuint32_t IFE9:1;
+ vuint32_t IFE8:1;
+ vuint32_t IFE7:1;
+ vuint32_t IFE6:1;
+ vuint32_t IFE5:1;
+ vuint32_t IFE4:1;
+ vuint32_t IFE3:1;
+ vuint32_t IFE2:1;
+ vuint32_t IFE1:1;
+ vuint32_t IFE0:1;
+ } B;
+ } IFER;
+
+ int32_t SIU_reserved3[3];
+
+ union { /* Pad Configuration Registers */
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t SME:1;
+ vuint16_t APC:1; //modified by safdar
+ vuint16_t APC0:1; //added by safdar
+ vuint16_t PA:2;
+ vuint16_t OBE:1;
+ vuint16_t IBE:1;
+ vuint16_t DCS:2;
+ vuint16_t ODE:1;
+ vuint16_t HYS:1;
+ vuint16_t SRC:2;
+ vuint16_t WPE:1;
+ vuint16_t WPS:1;
+ } B;
+ } PCR[149];
+
+ int16_t SIU_reserved12[363];
+ int32_t SIU_reserved4[48]; /* {0x500-0x440}/0x4 */
+
+ union { /* Pad Selection for Multiplexed Input Register */
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t PADSEL:4;
+ } B;
+ } PSMI[64];
+
+ int32_t SIU_reserved5[48]; /* {0x500-0x440}/0x4 */
+
+ union { /* GPIO Pin Data Output Registers */
+ vuint8_t R;
+ struct {
+ vuint8_t:7;
+ vuint8_t PDO:1;
+ } B;
+ } GPDO[152];
+
+ int32_t SIU_reserved6[90]; /* {0x500-0x440}/0x4 */
+
+ union { /* GPIO Pin Data Input Registers */
+ vuint8_t R;
+ struct {
+ vuint8_t:7;
+ vuint8_t PDI:1;
+ } B;
+ } GPDI[152];
+ int32_t SIU_reserved13[128];
+ int32_t SIU_reserved7[90]; /* {0xC00-0xA00}/0x4 */
+
+ union { /* Parallel GPIO Pin Data Output Register */
+ vuint32_t R;
+ struct {
+ vuint32_t PPD0:32;
+ } B;
+ } PGPDO[5];
+
+ int32_t SIU_reserved8[11]; /* {0xC00-0xA00}/0x4 */
+
+ union { /* Parallel GPIO Pin Data Input Register */
+ vuint32_t R;
+ struct {
+ vuint32_t PPDI:32;
+ } B;
+ } PGPDI[5];
+
+ int32_t SIU_reserved9[11]; /* {0xC00-0xA00}/0x4 */
+
+
+ union { /* Masked Parallel GPIO Pin Data Out Register */
+ vuint32_t R;
+ struct {
+ vuint32_t MASK:16;
+ vuint32_t MPPDO:16;
+ } B;
+ } MPGPDO[10];
+
+ int32_t SIU_reserved10[214]; /* {0x1000-0x0D00}/0x4 */
+
+ union { /* Interrupt Filter Maximum Counter Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t MAXCNT:4;
+ } B;
+ } IFMC[24];
+
+ int32_t SIU_reserved11[8]; /* {0x1000-0x0D00}/0x4 */
+
+ union { /* Interrupt Filter Clock Prescaler Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t IFCP:4;
+ } B;
+ } IFCPR;
+
+ }; /* end of SIU_tag */
+/****************************************************************************/
+/* MODULE : SSCM */
+/****************************************************************************/
+ struct SSCM_tag {
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t NXEN:1;
+ vuint16_t:1;
+ vuint16_t SEC:1;
+ vuint16_t:1;
+ vuint16_t BMODE:3;
+ vuint16_t DMID:1;
+ vuint16_t ABD:1;
+ vuint16_t:3;
+ } B;
+ } STATUS; /* Status Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SRAMSIZE:5;
+ vuint16_t IFLASHSIZE:5;
+ vuint16_t IVLD:1;
+ vuint16_t DFLASHSIZE:4;
+ vuint16_t DVLD:1;
+ } B;
+ } MEMCONFIG; /* System Memory Configuration Register */
+
+ int16_t SSCM_reserved;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:14;
+ vuint16_t PAE:1;
+ vuint16_t RAE:1;
+ } B;
+ } ERROR; /* Error Configuration Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:13;
+ vuint16_t DEBUG_MODE:3;
+ } B;
+ } DEBUGPORT; /* Debug Status Port Register */
+
+ int16_t SSCM_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PWD_HI:32;
+ } B;
+ } PWCMPH; /* Password Comparison Register High Word */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PWD_LO:32;
+ } B;
+ } PWCMPL; /* Password Comparison Register Low Word */
+
+ }; /* end of SSCM_tag */
+/****************************************************************************/
+/* MODULE : STM */
+/****************************************************************************/
+ struct STM_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CPS:8;
+ vuint32_t:6;
+ vuint32_t FRZ:1;
+ vuint32_t TEN:1;
+ } B;
+ } CR0; /* STM Control Register */
+
+ union {
+ vuint32_t R;
+ } CNT0; /* STM Count Register */
+
+ int32_t STM_reserved[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR0; /* STM Channel Control Register 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR0; /* STM Channel Interrupt Register 0 */
+
+ union {
+ vuint32_t R;
+ } CMP0; /* STM Channel Compare Register 0 */
+
+ int32_t STM_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR1; /* STM Channel Control Register 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR1; /* STM Channel Interrupt Register 1 */
+
+ union {
+ vuint32_t R;
+ } CMP1; /* STM Channel Compare Register 1 */
+
+ int32_t STM_reserved2;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR2; /* STM Channel Control Register 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR2; /* STM Channel Interrupt Register 2 */
+
+ union {
+ vuint32_t R;
+ } CMP2; /* STM Channel Compare Register 2 */
+
+ int32_t STM_reserved3;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR3; /* STM Channel Control Register 3 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR3; /* STM Channel Interrupt Register 3 */
+
+ union {
+ vuint32_t R;
+ } CMP3; /* STM Channel Compare Register 3 */
+
+ }; /* end of STM_tag */
+/****************************************************************************/
+/* MODULE : SWT */
+/****************************************************************************/
+ struct SWT_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MAP0:1;
+ vuint32_t MAP1:1;
+ vuint32_t MAP2:1;
+ vuint32_t MAP3:1;
+ vuint32_t MAP4:1;
+ vuint32_t MAP5:1;
+ vuint32_t MAP6:1;
+ vuint32_t MAP7:1;
+ vuint32_t:15;
+ vuint32_t RIA:1;
+ vuint32_t WND:1;
+ vuint32_t ITR:1;
+ vuint32_t HLK:1;
+ vuint32_t SLK:1;
+ vuint32_t CSL:1;
+ vuint32_t STP:1;
+ vuint32_t FRZ:1;
+ vuint32_t WEN:1;
+ } B;
+ } CR; /* SWT Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t TIF:1;
+ } B;
+ } IR; /* SWT Interrupt Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t WTO:32;
+ } B;
+ } TO; /* SWT Time-Out Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t WST:32;
+ } B;
+ } WN; /* SWT Window Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t WSC:16;
+ } B;
+ } SR; /* SWT Service Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CNT:32;
+ } B;
+ } CO; /* SWT Counter Output Register */
+
+ }; /* end of SWT_tag */
+/****************************************************************************/
+/* MODULE : WKUP */
+/****************************************************************************/
+ struct WKUP_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t NIF0:1;
+ vuint32_t NOVF0:1;
+ vuint32_t:6;
+ vuint32_t NIF1:1;
+ vuint32_t NOVF1:1;
+ vuint32_t:6;
+ vuint32_t NIF2:1;
+ vuint32_t NOVF2:1;
+ vuint32_t:6;
+ vuint32_t NIF3:1;
+ vuint32_t NOVF3:1;
+ vuint32_t:6;
+ } B;
+ } NSR; /* NMI Status Register */
+
+ int32_t WKUP_reserved;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t NLOCK0:1;
+ vuint32_t NDSS0:2;
+ vuint32_t NWRE0:1;
+ vuint32_t:1;
+ vuint32_t NREE0:1;
+ vuint32_t NFEE0:1;
+ vuint32_t NFE0:1;
+ vuint32_t NLOCK1:1;
+ vuint32_t NDSS1:2;
+ vuint32_t NWRE1:1;
+ vuint32_t:1;
+ vuint32_t NREE1:1;
+ vuint32_t NFEE1:1;
+ vuint32_t NFE1:1;
+ vuint32_t NLOCK2:1;
+ vuint32_t NDSS2:2;
+ vuint32_t NWRE2:1;
+ vuint32_t:1;
+ vuint32_t NREE2:1;
+ vuint32_t NFEE2:1;
+ vuint32_t NFE2:1;
+ vuint32_t NLOCK3:1;
+ vuint32_t NDSS3:2;
+ vuint32_t NWRE3:1;
+ vuint32_t:1;
+ vuint32_t NREE3:1;
+ vuint32_t NFEE3:1;
+ vuint32_t NFE3:1;
+ } B;
+ } NCR; /* NMI Configuration Register */
+
+ int32_t WKUP_reserved1[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EIF:32;
+ } B;
+ } WISR; /* Wakeup/Interrupt Status Flag Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EIRE:32;
+ } B;
+ } IRER; /* Interrupt Request Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t WRE:32;
+ } B;
+ } WRER; /* Wakeup Request Enable Register */
+
+ int32_t WKUP_reserved2[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t IREE:32;
+ } B;
+ } WIREER; /* Wakeup/Interrupt Rising-Edge Event Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t IFEE:32;
+ } B;
+ } WIFEER; /* Wakeup/Interrupt Falling-Edge Event Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t IFE:32;
+ } B;
+ } WIFER; /* Wakeup/Interrupt Filter Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t IPUE:32;
+ } B;
+ } WIPUER; /* Wakeup/Interrupt Pullup Enable Register */
+
+ }; /* end of WKUP_tag */
+/****************************************************************************/
+/* MODULE : LINFLEX */
+/****************************************************************************/
+
+ struct LINFLEX_tag {
+
+ int16_t LINFLEX_reserved1;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CCD:1;
+ vuint16_t CFD:1;
+ vuint16_t LASE:1;
+ vuint16_t AWUM:1; // LCH vuint16_t AUTOWU:1;
+ vuint16_t MBL:4;
+ vuint16_t BF:1;
+ vuint16_t SLFM:1;
+ vuint16_t LBKM:1;
+ vuint16_t MME:1;
+ vuint16_t SBDT:1; // LCH vuint16_t SSBL:1;
+ vuint16_t RBLM:1;
+ vuint16_t SLEEP:1;
+ vuint16_t INIT:1;
+ } B;
+ } LINCR1; /* LINFLEX LIN Control Register 1 */
+
+ int16_t LINFLEX_reserved2;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SZIE:1;
+ vuint16_t OCIE:1;
+ vuint16_t BEIE:1;
+ vuint16_t CEIE:1;
+ vuint16_t HEIE:1;
+ vuint16_t:2;
+ vuint16_t FEIE:1;
+ vuint16_t BOIE:1;
+ vuint16_t LSIE:1;
+ vuint16_t WUIE:1;
+ vuint16_t DBFIE:1;
+ vuint16_t DBEIE:1;
+ vuint16_t DRIE:1;
+ vuint16_t DTIE:1;
+ vuint16_t HRIE:1;
+ } B;
+ } LINIER; /* LINFLEX LIN Interrupt Enable Register */
+
+ int16_t LINFLEX_reserved3;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t LINS:4;
+ vuint16_t:2;
+ vuint16_t RMB:1;
+ vuint16_t:1;
+ vuint16_t RBSY:1; // LCH vuint16_t RXBUSY:1;
+ vuint16_t RPS:1; // LCH vuint16_t RDI:1;
+ vuint16_t WUF:1;
+ vuint16_t DBFF:1;
+ vuint16_t DBEF:1;
+ vuint16_t DRF:1;
+ vuint16_t DTF:1;
+ vuint16_t HRF:1;
+ } B;
+ } LINSR; /* LINFLEX LIN Status Register */
+
+ int16_t LINFLEX_reserved4;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SZF:1;
+ vuint16_t OCF:1;
+ vuint16_t BEF:1;
+ vuint16_t CEF:1;
+ vuint16_t SFEF:1;
+ vuint16_t SDEF:1;
+ vuint16_t IDPEF:1;
+ vuint16_t FEF:1;
+ vuint16_t BOF:1;
+ vuint16_t:6;
+ vuint16_t NF:1;
+ } B;
+ } LINESR; /* LINFLEX LIN Error Status Register */
+
+ int16_t LINFLEX_reserved5;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t TDFL:2;
+ vuint16_t:1;
+ vuint16_t RDFL:2;
+ vuint16_t RFBM:1;
+ vuint16_t TFBM:1;
+ vuint16_t WL1:1;
+ vuint16_t OP1:1;
+ vuint16_t RXEN:1;
+ vuint16_t TXEN:1;
+ vuint16_t OP0:1; //LCH vuint16_t PARITYODD:1;
+ vuint16_t PCE:1;
+ vuint16_t WL0:1;
+ vuint16_t UART:1;
+ } B;
+ } UARTCR; /* LINFLEX UART Mode Control Register */
+
+ int16_t LINFLEX_reserved6;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SZF:1;
+ vuint16_t OCF:1;
+ vuint16_t PE:4;
+ vuint16_t RMB:1;
+ vuint16_t FEF:1;
+ vuint16_t BOF:1;
+ vuint16_t RPS:1; // LCH vuint16_t RDI:1;
+ vuint16_t WUF:1;
+ vuint16_t:2;
+ vuint16_t DRF:1;
+ vuint16_t DTF:1;
+ vuint16_t NF:1;
+ } B;
+ } UARTSR; /* LINFLEX UART Mode Status Register */
+
+ int16_t LINFLEX_reserved7;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t LTOM:1; //LCH vuint16_t MODE:1;
+ vuint16_t IOT:1;
+ vuint16_t TOCE:1;
+ vuint16_t CNT:8;
+ } B;
+ } LINTCSR; /* LINFLEX LIN Time-Out Control Status Register */
+
+ int16_t LINFLEX_reserved8;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t OC2:8;
+ vuint16_t OC1:8;
+ } B;
+ } LINOCR; /* LINFLEX LIN Output Compare Register */
+
+ int16_t LINFLEX_reserved9;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t RTO:4; // LCH vuint16_t RTC:4;
+ vuint16_t:1;
+ vuint16_t HTO:7; // LCH vuint16_t HTC:7;
+ } B;
+ } LINTOCR; /* LINFLEX LIN Output Compare Register */
+
+ int16_t LINFLEX_reserved10;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t DIV_F:4; // LCH vuint16_t FBR:4;
+ } B;
+ } LINFBRR; /* LINFLEX LIN Fractional Baud Rate Register */
+
+ int16_t LINFLEX_reserved11;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:3;
+ vuint16_t DIV_M:13; // LCH vuint16_t IBR:13;
+ } B;
+ } LINIBRR; /* LINFLEX LIN Integer Baud Rate Register */
+
+ int16_t LINFLEX_reserved12;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t CF:8;
+ } B;
+ } LINCFR; /* LINFLEX LIN Checksum Field Register */
+
+ int16_t LINFLEX_reserved13;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t IOBE:1;
+ vuint16_t IOPE:1;
+ vuint16_t WURQ:1;
+ vuint16_t DDRQ:1;
+ vuint16_t DTRQ:1;
+ vuint16_t ABRQ:1;
+ vuint16_t HTRQ:1;
+ vuint16_t:8;
+ } B;
+ } LINCR2; /* LINFLEX LIN Control Register 2 */
+
+ int16_t LINFLEX_reserved14;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t DFL:6;
+ vuint16_t DIR:1;
+ vuint16_t CCS:1;
+ vuint16_t:2; // LCH vuint16_t:1;
+ vuint16_t ID:6;
+ } B;
+ } BIDR; /* LINFLEX Buffer Identifier Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DATA3:8;
+ vuint32_t DATA2:8;
+ vuint32_t DATA1:8;
+ vuint32_t DATA0:8;
+ } B;
+ } BDRL; /* LINFLEX Buffer Data Register Least Significant */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DATA7:8;
+ vuint32_t DATA6:8;
+ vuint32_t DATA5:8;
+ vuint32_t DATA4:8;
+ } B;
+ } BDRM; /* LINFLEX Buffer Data Register Most Significant */
+
+ int16_t LINFLEX_reserved15;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t FACT:8;
+ } B;
+ } IFER; /* LINFLEX Identifier Filter Enable Register */
+
+ int16_t LINFLEX_reserved16;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t IFMI:4;
+ } B;
+ } IFMI; /* LINFLEX Identifier Filter Match Index Register */
+
+ int16_t LINFLEX_reserved17;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t IFM:4;
+ } B;
+ } IFMR; /* LINFLEX Identifier Filter Mode Register */
+
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t:3;
+ vuint32_t DFL:3;
+ vuint32_t DIR:1;
+ vuint32_t CCS:1;
+ vuint32_t:2;
+ vuint32_t ID:6;
+ } B;
+ } IFCR[16];
+
+ int32_t LINFLEX_reserved18;//GCR egister commented
+
+
+ int16_t LINFLEX_reserved19;//UARTPTO upper 16 bits reserved
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t PTO:12;
+ } B;
+ }UARTPTO;
+
+ int32_t LINFLEX_reserved20;//UARTCTO egister commented
+
+ int16_t LINFLEX_reserved21;
+
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t DTE15:1;
+ vuint16_t DTE14:1;
+ vuint16_t DTE13:1;
+ vuint16_t DTE12:1;
+ vuint16_t DTE11:1;
+ vuint16_t DTE10:1;
+ vuint16_t DTE9:1;
+ vuint16_t DTE8:1;
+ vuint16_t DTE7:1;
+ vuint16_t DTE6:1;
+ vuint16_t DTE5:1;
+ vuint16_t DTE4:1;
+ vuint16_t DTE3:1;
+ vuint16_t DTE2:1;
+ vuint16_t DTE1:1;
+ vuint16_t DTE0:1;
+ } B;
+ } DMATXE;
+ int16_t LINFLEX_reserved22;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t DRE15:1;
+ vuint16_t DRE14:1;
+ vuint16_t DRE13:1;
+ vuint16_t DRE12:1;
+ vuint16_t DRE11:1;
+ vuint16_t DRE10:1;
+ vuint16_t DRE9:1;
+ vuint16_t DRE8:1;
+ vuint16_t DRE7:1;
+ vuint16_t DRE6:1;
+ vuint16_t DRE5:1;
+ vuint16_t DRE4:1;
+ vuint16_t DRE3:1;
+ vuint16_t DRE2:1;
+ vuint16_t DRE1:1;
+ vuint16_t DRE0:1;
+
+ } B;
+ } DMARXE;
+
+
+
+ }; /* end of LINFLEX_tag */
+
+/****************************************************************************/
+/* MODULE : ME */
+/****************************************************************************/
+struct ME_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CURRENTMODE:4;
+ vuint32_t MTRANS:1;
+ vuint32_t DC:1;
+ vuint32_t:2;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVR:1;
+ vuint32_t DFLA:2;
+ vuint32_t CFLA:2;
+ vuint32_t SSCLK:9;
+ vuint32_t PLL:1;
+ vuint32_t OSC:1;
+ vuint32_t RC:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } GS; /* Global Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TARGETMODE:4;
+ vuint32_t:12;
+ vuint32_t KEY:16;
+ } B;
+ } MCTL; /* Mode Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:18;
+ vuint32_t STANDBY0:1;
+ vuint32_t:2;
+ vuint32_t STOP0:1;
+ vuint32_t:1;
+ vuint32_t HALT0:1;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RESET:1;
+ } B;
+ } MER; /* Mode Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t ICONF:1;
+ vuint32_t IMODE:1;
+ vuint32_t SAFE:1;
+ vuint32_t MTC:1;
+ } B;
+ } IS; /* Interrupt Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t ICONF:1;
+ vuint32_t IMODE:1;
+ vuint32_t SAFE:1;
+ vuint32_t MTC:1;
+ } B;
+ } IM; /* Interrupt Mask Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:27;
+ vuint32_t MTI:1;
+ vuint32_t MRI:1;
+ vuint32_t DMA:1;
+ vuint32_t NMA:1;
+ vuint32_t SEA:1;
+ } B;
+ } IMTS; /* Invalid Mode Transition Status Register */
+
+ int32_t ME_reserved0[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } RESET; /* Reset Mode Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } TEST; /* Test Mode Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } SAFE; /* Safe Mode Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } DRUN; /* DRUN Mode Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } RUN[4]; /* RUN 0->4 Mode Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } HALT0; /* HALT0 Mode Configuration Register */
+
+ int32_t ME_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } STOP0; /* STOP0 Mode Configuration Register */
+
+ int32_t ME_reserved2[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } STANDBY0; /* STANDBY0 Mode Configuration Register */
+
+ int32_t ME_reserved3[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PERIPH:32;
+ } B;
+ } PS[5]; /* Peripheral Status 0->4 Register */
+
+ int32_t ME_reserved4[3];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RESET:1;
+ } B;
+ } RUNPC[8]; /* RUN Peripheral Configuration 0->7 Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:18;
+ vuint32_t STANDBY0:1;
+ vuint32_t:2;
+ vuint32_t STOP0:1;
+ vuint32_t:1;
+ vuint32_t HALT0:1;
+ vuint32_t:8;
+ } B;
+ } LPPC[8]; /* Low Power Peripheral Configuration 0->7 Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t DBGP:1;
+ vuint8_t DBGF:1;
+ vuint8_t LPCFG:1;
+ vuint8_t RUNCFG:1;
+ } B;
+ } PCTL[144]; /* Peripheral Control 0->143 Register */
+
+ /************************************/
+ /* Register Protection */
+ /************************************/
+ int32_t ME_reserved5[1964]; /* {0x2000-0x0150}/0x4 = 0x7AC */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CURRENTMODE:4;
+ vuint32_t MTRANS:1;
+ vuint32_t DC:1;
+ vuint32_t:2;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVR:1;
+ vuint32_t DFLA:2;
+ vuint32_t CFLA:2;
+ vuint32_t SSCLK:9;
+ vuint32_t PLL:1;
+ vuint32_t OSC:1;
+ vuint32_t RC:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } GS_LOCK; /* Global Status Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TARGETMODE:4;
+ vuint32_t:12;
+ vuint32_t KEY:16;
+ } B;
+ } MCTL_LOCK; /* Mode Control Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:18;
+ vuint32_t STANDBY0:1;
+ vuint32_t:2;
+ vuint32_t STOP0:1;
+ vuint32_t:1;
+ vuint32_t HALT0:1;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RESET:1;
+ } B;
+ } ME_LOCK; /* Mode Enable Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t ICONF:1;
+ vuint32_t IMODE:1;
+ vuint32_t SAFE:1;
+ vuint32_t MTC:1;
+ } B;
+ } IS_LOCK; /* Interrupt Status Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t ICONF:1;
+ vuint32_t IMODE:1;
+ vuint32_t SAFE:1;
+ vuint32_t MTC:1;
+ } B;
+ } IM_LOCK; /* Interrupt Mask Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:27;
+ vuint32_t MTI:1;
+ vuint32_t MRI:1;
+ vuint32_t DMA:1;
+ vuint32_t NMA:1;
+ vuint32_t SEA:1;
+ } B;
+ } IMTS_LOCK; /* Invalid Mode Transition Status Register Lock */
+
+ int32_t ME_reserved6[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } RESET_LOCK; /* Reset Mode Configuration Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } TEST_LOCK; /* Test Mode Configuration Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } SAFE_LOCK; /* Safe Mode Configuration Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } DRUN_LOCK; /* DRUN Mode Configuration Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } RUN_LOCK[4]; /* RUN 0->4 Mode Configuration Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } HALT0_LOCK; /* HALT0 Mode Configuration Register Lock */
+
+ int32_t ME_reserved7;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } STOP0_LOCK; /* STOP0 Mode Configuration Register Lock */
+
+ int32_t ME_reserved8[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } STANDBY0_LOCK; /* STANDBY0 Mode Configuration Register Lock */
+
+ int32_t ME_reserved9[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PERIPH:32;
+ } B;
+ } PS_LOCK[5]; /* Peripheral Status 0->4 Register Lock */
+
+ int32_t ME_reserved10[3];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RESET:1;
+ } B;
+ } RUNPC_LOCK[8]; /* RUN Peripheral Configuration 0->7 Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:18;
+ vuint32_t STANDBY0:1;
+ vuint32_t:2;
+ vuint32_t STOP0:1;
+ vuint32_t:1;
+ vuint32_t HALT0:1;
+ vuint32_t:8;
+ } B;
+ } LPPC_LOCK[8]; /* Low Power Peripheral Configuration 0->7 Register Lock */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t DBGP:1;
+ vuint8_t DBGF:1;
+ vuint8_t LPCFG:1;
+ vuint8_t RUNCFG:1;
+ } B;
+ } PCTL_LOCK[144]; /* Peripheral Control 0->143 Register Lock */
+
+ int32_t ME_reserved11[1452]; /* {0x3800-0x2150}/0x4 = 0x5AC */
+
+ union { /* Soft Lock Bit Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SLB0:4;
+ vuint32_t:4;
+ vuint32_t SLB1:4;
+ vuint32_t:4;
+ vuint32_t SLB2:4;
+ vuint32_t:4;
+ vuint32_t SLB3:4;
+ } B;
+ } SLBR[384];
+
+ int32_t ME_reserved12[127]; /* {0x3FFC-0x3E00}/0x4 = 0x07F */
+
+ union { /* Global Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t HLB:1;
+ vuint32_t:7;
+ vuint32_t SOB:1;
+ vuint32_t:23;
+ } B;
+ } GCR;
+
+ }; /* end of ME_tag */
+
+
+/****************************************************************************/
+/* MODULE : CGM */
+/****************************************************************************/
+ struct CGM_tag {
+
+ /* The CGM provides a unified register interface, enabling access to
+ all clock sources:
+
+ Base Address | Clock Sources
+ -----------------------------
+ 0xC3FE0000 | FXOSC_CTL
+ ---------- | Reserved
+ 0xC3FE0040 | SXOSC_CTL
+ 0xC3FE0060 | FIRC_CTL
+ 0xC3FE0080 | SIRC_CTL
+ 0xC3FE00A0 | FMPLL_0
+ ---------- | Reserved
+ 0xC3FE0100 | CMU_0
+
+ */
+
+ /************************************/
+ /* FXOSC_CTL @ CGM base address + 0x0000 */
+ /************************************/
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OSCBYP:1;
+ vuint32_t:7;
+ vuint32_t EOCV:8;
+ vuint32_t M_OSC:1;
+ vuint32_t:2;
+ vuint32_t OSCDIV:5;
+ vuint32_t I_OSC:1;
+ vuint32_t:7;
+ } B;
+ } FXOSC_CTL; /* Fast OSC Control Register */
+
+ /************************************/
+ /* SXOSC_CTL @ CGM base address + 0x0040 */
+ /************************************/
+ int32_t CGM_reserved0[15]; /* (0x040 - 0x004)/4 = 0x0F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OSCBYP:1;
+ vuint32_t:7;
+ vuint32_t EOCV:8;
+ vuint32_t M_OSC:1;
+ vuint32_t:2;
+ vuint32_t OSCDIV:5;
+ vuint32_t I_OSC:1;
+ vuint32_t:5;
+ vuint32_t S_OSC:1;
+ vuint32_t OSCON:1;
+ } B;
+ } SXOSC_CTL; /* Slow OSC Control Register */
+
+ /************************************/
+ /* FIRC_CTL @ CGM base address + 0x0060 */
+ /************************************/
+ int32_t CGM_reserved1[7]; /* (0x060 - 0x044)/4 = 0x07 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:10;
+ vuint32_t RCTRIM:6;
+ vuint32_t:3;
+ vuint32_t RCDIV:5;
+ vuint32_t:8;
+ } B;
+ } FIRC_CTL; /* Fast IRC Control Register */
+
+ /****************************************/
+ /* SIRC_CTL @ CGM base address + 0x0080 */
+ /****************************************/
+ int32_t CGM_reserved2[7]; /* (0x080 - 0x064)/4 = 0x07 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:11;
+ vuint32_t RCTRIM:5;
+ vuint32_t:3;
+ vuint32_t RCDIV:5;
+ vuint32_t:3;
+ vuint32_t S_SIRC:1;
+ vuint32_t:3;
+ vuint32_t SIRCON_STDBY:1;
+ } B;
+ } SIRC_CTL; /* Slow IRC Control Register */
+
+ /*************************************/
+ /* FMPLL @ CGM base address + 0x00A0 */
+ /*************************************/
+ int32_t CGM_reserved3[7]; /* (0x0A0 - 0x084)/4 = 0x07 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:2;
+ vuint32_t IDF:4;
+ vuint32_t ODF:2;
+ vuint32_t:1;
+ vuint32_t NDIV:7;
+ vuint32_t:7;
+ vuint32_t EN_PLL_SW:1;
+ vuint32_t MODE:1;
+ vuint32_t UNLOCK_ONCE:1;
+ vuint32_t:1;
+ vuint32_t I_LOCK:1;
+ vuint32_t S_LOCK:1;
+ vuint32_t PLL_FAIL_MASK:1;
+ vuint32_t PLL_FAIL_FLAG:1;
+ vuint32_t:1;
+ } B;
+ } FMPLL_CR; /* FMPLL Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t STRB_BYPASS:1;
+ vuint32_t:1;
+ vuint32_t SPRD_SEL:1;
+ vuint32_t MOD_PERIOD:13;
+ vuint32_t FM_EN:1;
+ vuint32_t INC_STEP:15;
+ } B;
+ } FMPLL_MR; /* FMPLL Modulation Register */
+
+ /************************************/
+ /* CMU @ CGM base address + 0x0100 */
+ /************************************/
+ int32_t CGM_reserved5[22]; /* (0x100 - 0x0A8)/4 = 0x16 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t SFM:1;
+ vuint32_t:13;
+ vuint32_t CLKSEL1:2;
+ vuint32_t:5;
+ vuint32_t RCDIV:2;
+ vuint32_t CME_A:1;
+ } B;
+ } CMU_CSR; /* Control Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t FD:20;
+ } B;
+ } CMU_FDR; /* Frequency Display Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t HFREF_A:12;
+ } B;
+ } CMU_HFREFR_A; /* High Frequency Reference Register PLL_A Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t LFREF_A:12;
+ } B;
+ } CMU_LFREFR_A; /* Low Frequency Reference Register PLL_A Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t FLCI_A:1;
+ vuint32_t FHHI_A:1;
+ vuint32_t FLLI_A:1;
+ vuint32_t OLRI:1;
+ } B;
+ } CMU_ISR; /* Interrupt Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } CMU_IMR; /* Interrupt Mask Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t MD:20;
+ } B;
+ } CMU_MDR; /* Measurement Duration Register */
+
+ /************************************/
+ /* CGM General Registers @ CGM base address + 0x0370 */
+ /************************************/
+ int32_t CGM_reserved7[149]; /* (0x370 - 0x11C)/4 = 0x95 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t EN:1;
+ } B;
+ } OC_EN; /* Output Clock Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:2;
+ vuint32_t SELDIV:2;
+ vuint32_t SELCTL:4;
+ vuint32_t:24;
+ } B;
+ } OCDS_SC; /* Output Clock Division Select Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SELSTAT:4;
+ vuint32_t:24;
+ } B;
+ } SC_SS; /* System Clock Select Status */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t DE:1;
+ vuint8_t:3;
+ vuint8_t DIV:4;
+ } B;
+ } SC_DC[3]; /* System Clock Divider Configuration 0->2 */
+
+ }; /* end of CGM_tag */
+/****************************************************************************/
+/* MODULE : RGM */
+/****************************************************************************/
+ struct RGM_tag {
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t F_EXR:1;
+ vuint16_t:3;
+ vuint16_t F_CMU1_FHL:1;
+ vuint16_t:1;
+ vuint16_t F_PLL1:1;
+ vuint16_t F_FLASH:1;
+ vuint16_t F_LVD45:1;
+ vuint16_t F_CMU0_FHL:1;
+ vuint16_t F_CMU0_OLR:1;
+ vuint16_t F_PLL0:1;
+ vuint16_t F_CHKSTOP:1;
+ vuint16_t F_SOFT:1;
+ vuint16_t F_CORE:1;
+ vuint16_t F_JTAG:1;
+ } B;
+ } FES; /* Functional Event Status */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t POR:1;
+ vuint16_t:7;
+ vuint16_t F_COMP:1;
+ vuint16_t F_LVD27_IO:1;
+ vuint16_t F_LVD27_FLASH:1;
+ vuint16_t F_LVD27_VREG:1;
+ vuint16_t F_LVD27:1;
+ vuint16_t F_SWT:1;
+ vuint16_t F_LVD12_PD1:1;
+ vuint16_t F_LVD12_PD0:1;
+ } B;
+ } DES; /* Destructive Event Status */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t D_EXR:1;
+ vuint16_t:3;
+ vuint16_t D_CMU1_FHL:1;
+ vuint16_t:1;
+ vuint16_t D_PLL1:1;
+ vuint16_t D_FLASH:1;
+ vuint16_t D_LVD45:1;
+ vuint16_t D_CMU0_FHL:1;
+ vuint16_t D_CMU0_OLR:1;
+ vuint16_t D_PLL0:1;
+ vuint16_t D_CHKSTOP:1;
+ vuint16_t D_SOFT:1;
+ vuint16_t D_CORE:1;
+ vuint16_t D_JTAG:1;
+ } B;
+ } FERD; /* Functional Event Reset Disable */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t D_COMP:1;
+ vuint16_t D_LVD27_IO:1;
+ vuint16_t D_LVD27_FLASH:1;
+ vuint16_t D_LVD27_VREG:1;
+ vuint16_t D_LVD27:1;
+ vuint16_t D_SWT:1;
+ vuint16_t D_LVD12_PD1:1;
+ vuint16_t D_LVD12_PD0:1;
+ } B;
+ } DERD; /* Destructive Event Reset Disable */
+
+ int16_t RGM_reserved0[4];
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t AR_CMU1_FHL:1;
+ vuint16_t:1;
+ vuint16_t AR_PLL1:1;
+ vuint16_t AR_FLASH:1;
+ vuint16_t AR_LVD45:1;
+ vuint16_t AR_CMU0_FHL:1;
+ vuint16_t AR_CMU0_OLR:1;
+ vuint16_t AR_PLL0:1;
+ vuint16_t AR_CHKSTOP:1;
+ vuint16_t AR_SOFT:1;
+ vuint16_t AR_CORE:1;
+ vuint16_t AR_JTAG:1;
+ } B;
+ } FEAR; /* Functional Event Alternate Request */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t AR_COMP:1;
+ vuint16_t AR_LVD27_IO:1;
+ vuint16_t AR_LVD27_FLASH:1;
+ vuint16_t AR_LVD27_VREG:1;
+ vuint16_t AR_LVD27:1;
+ vuint16_t AR_SWT:1;
+ vuint16_t AR_LVD12_PD1:1;
+ vuint16_t AR_LVD12_PD0:1;
+ } B;
+ } DEAR; /* Destructive Event Alternate Request */
+
+ int16_t RGM_reserved1[2];
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:7;
+ vuint16_t SS_FLASH:1;
+ vuint16_t SS_LVD45:1;
+ vuint16_t SS_CMU0_FHL:1;
+ vuint16_t SS_CMU0_OLR:1;
+ vuint16_t SS_PLL0:1;
+ vuint16_t SS_CHKSTOP:1;
+ vuint16_t SS_SOFT:1;
+ vuint16_t SS_CORE:1;
+ vuint16_t SS_JTAG:1;
+ } B;
+ } FESS; /* Functional Event Short Sequence */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t BOOT:1;
+ vuint16_t:4;
+ vuint16_t DRUND_FLA:1;
+ vuint16_t:1;
+ vuint16_t DRUNC_FLA:1;
+ } B;
+ } STDBY; /* STANDBY reset sequence */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:7;
+ vuint16_t BE_FLASH:1;
+ vuint16_t BE_LVD45:1;
+ vuint16_t BE_CMU0_FHL:1;
+ vuint16_t BE_CMU0_OLR:1;
+ vuint16_t BE_PLL0:1;
+ vuint16_t BE_CHKSTOP:1;
+ vuint16_t BE_SOFT:1;
+ vuint16_t BE_CORE:1;
+ vuint16_t BE_JTAG:1;
+ } B;
+ } FBRE; /* Functional Bidirectional Reset Enable */
+
+ }; /* end of RGM_tag */
+/****************************************************************************/
+/* MODULE : PCU */
+/****************************************************************************/
+ struct PCU_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:18;
+ vuint32_t STBY0:1;
+ vuint32_t:2;
+ vuint32_t STOP0:1;
+ vuint32_t:1;
+ vuint32_t HALT0:1;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RST:1;
+ } B;
+ } PCONF[16]; /* Power domain 0-15 configuration register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t PD15:1;
+ vuint32_t PD14:1;
+ vuint32_t PD13:1;
+ vuint32_t PD12:1;
+ vuint32_t PD11:1;
+ vuint32_t PD10:1;
+ vuint32_t PD9:1;
+ vuint32_t PD8:1;
+ vuint32_t PD7:1;
+ vuint32_t PD6:1;
+ vuint32_t PD5:1;
+ vuint32_t PD4:1;
+ vuint32_t PD3:1;
+ vuint32_t PD2:1;
+ vuint32_t PD1:1;
+ vuint32_t PD0:1;
+ } B;
+ } PSTAT; /* Power Domain Status Register */
+
+ int32_t PCU_reserved0[15]; /* {0x0080-0x0044}/0x4 = 0xF */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:15;
+ vuint32_t MASK_LVDHV5:1;
+ } B;
+ } VCTL; /* Voltage Regulator Control Register */
+
+ }; /* end of PCU_tag */
+
+/****************************************************************************/
+/* MODULE : CTUL */
+/****************************************************************************/
+ struct CTUL_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t:8;
+ vuint32_t TRGIEN:1;
+ vuint32_t TRGI:1;
+ vuint32_t:6;
+ } B;
+ } CSR; /* Control Status Register */
+
+ int32_t CTU_reserved0[11];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t TM:1;
+ vuint32_t CLR_FLAG:1;
+ vuint32_t:5;
+ vuint32_t ADC_SEL:1;
+ vuint32_t:1;
+ vuint32_t CHANNELVALUE:7;
+ } B;
+ } EVTCFGR[64]; /* Event Configuration Register */
+
+ }; /* end of CTUL_tag */
+
+/****************************************************************************/
+/* MODULE : EMIOS */
+/****************************************************************************/
+ struct EMIOS_CHANNEL_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CADR:16;
+ } B;
+ } CADR; /* Channel A Data Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CBDR:16;
+ } B;
+ } CBDR; /* Channel B Data Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CCNTR:16;
+ } B;
+ } CCNTR; /* Channel Counter Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t FREN:1;
+ vuint32_t:3;
+ vuint32_t UCPRE:2;
+ vuint32_t UCPEN:1;
+ vuint32_t DMA:1;
+ vuint32_t:1;
+ vuint32_t IF:4;
+ vuint32_t FCK:1;
+ vuint32_t FEN:1;
+ vuint32_t:3;
+ vuint32_t FORCMA:1;
+ vuint32_t FORCMB:1;
+ vuint32_t:1;
+ vuint32_t BSL:2;
+ vuint32_t EDSEL:1;
+ vuint32_t EDPOL:1;
+ vuint32_t MODE:7;
+ } B;
+ } CCR; /* Channel Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OVR:1;
+ vuint32_t:15;
+ vuint32_t OVFL:1;
+ vuint32_t:12;
+ vuint32_t UCIN:1;
+ vuint32_t UCOUT:1;
+ vuint32_t FLAG:1;
+ } B;
+ } CSR; /* Channel Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t ALTA:16;
+ } B;
+ } ALTCADR; /* Alternate Channel A Data Register */
+
+ uint32_t emios_channel_reserved[2];
+
+ }; /* end of EMIOS_CHANNEL_tag */
+
+ struct EMIOS_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ vuint32_t GTBE:1;
+ vuint32_t:1;
+ vuint32_t GPREN:1;
+ vuint32_t:10;
+ vuint32_t GPRE:8;
+ vuint32_t:8;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t F31:1;
+ vuint32_t F30:1;
+ vuint32_t F29:1;
+ vuint32_t F28:1;
+ vuint32_t F27:1;
+ vuint32_t F26:1;
+ vuint32_t F25:1;
+ vuint32_t F24:1;
+ vuint32_t F23:1;
+ vuint32_t F22:1;
+ vuint32_t F21:1;
+ vuint32_t F20:1;
+ vuint32_t F19:1;
+ vuint32_t F18:1;
+ vuint32_t F17:1;
+ vuint32_t F16:1;
+ vuint32_t F15:1;
+ vuint32_t F14:1;
+ vuint32_t F13:1;
+ vuint32_t F12:1;
+ vuint32_t F11:1;
+ vuint32_t F10:1;
+ vuint32_t F9:1;
+ vuint32_t F8:1;
+ vuint32_t F7:1;
+ vuint32_t F6:1;
+ vuint32_t F5:1;
+ vuint32_t F4:1;
+ vuint32_t F3:1;
+ vuint32_t F2:1;
+ vuint32_t F1:1;
+ vuint32_t F0:1;
+ } B;
+ } GFR; /* Global FLAG Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OU31:1;
+ vuint32_t OU30:1;
+ vuint32_t OU29:1;
+ vuint32_t OU28:1;
+ vuint32_t OU27:1;
+ vuint32_t OU26:1;
+ vuint32_t OU25:1;
+ vuint32_t OU24:1;
+ vuint32_t OU23:1;
+ vuint32_t OU22:1;
+ vuint32_t OU21:1;
+ vuint32_t OU20:1;
+ vuint32_t OU19:1;
+ vuint32_t OU18:1;
+ vuint32_t OU17:1;
+ vuint32_t OU16:1;
+ vuint32_t OU15:1;
+ vuint32_t OU14:1;
+ vuint32_t OU13:1;
+ vuint32_t OU12:1;
+ vuint32_t OU11:1;
+ vuint32_t OU10:1;
+ vuint32_t OU9:1;
+ vuint32_t OU8:1;
+ vuint32_t OU7:1;
+ vuint32_t OU6:1;
+ vuint32_t OU5:1;
+ vuint32_t OU4:1;
+ vuint32_t OU3:1;
+ vuint32_t OU2:1;
+ vuint32_t OU1:1;
+ vuint32_t OU0:1;
+ } B;
+ } OUDR; /* Output Update Disable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CHDIS31:1;
+ vuint32_t CHDIS30:1;
+ vuint32_t CHDIS29:1;
+ vuint32_t CHDIS28:1;
+ vuint32_t CHDIS27:1;
+ vuint32_t CHDIS26:1;
+ vuint32_t CHDIS25:1;
+ vuint32_t CHDIS24:1;
+ vuint32_t CHDIS23:1;
+ vuint32_t CHDIS22:1;
+ vuint32_t CHDIS21:1;
+ vuint32_t CHDIS20:1;
+ vuint32_t CHDIS19:1;
+ vuint32_t CHDIS18:1;
+ vuint32_t CHDIS17:1;
+ vuint32_t CHDIS16:1;
+ vuint32_t CHDIS15:1;
+ vuint32_t CHDIS14:1;
+ vuint32_t CHDIS13:1;
+ vuint32_t CHDIS12:1;
+ vuint32_t CHDIS11:1;
+ vuint32_t CHDIS10:1;
+ vuint32_t CHDIS9:1;
+ vuint32_t CHDIS8:1;
+ vuint32_t CHDIS7:1;
+ vuint32_t CHDIS6:1;
+ vuint32_t CHDIS5:1;
+ vuint32_t CHDIS4:1;
+ vuint32_t CHDIS3:1;
+ vuint32_t CHDIS2:1;
+ vuint32_t CHDIS1:1;
+ vuint32_t CHDIS0:1;
+ } B;
+ } UCDIS; /* Disable Channel Register */
+
+ uint32_t emios_reserved1[4];
+
+ struct EMIOS_CHANNEL_tag CH[32];
+
+ }; /* end of EMIOS_tag */
+/****************************************************************************/
+/* MODULE : pit */
+/****************************************************************************/
+ struct PIT_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ } B;
+ } PITMCR;
+
+ uint32_t pit_reserved1[63]; /* (0x0100 - 0x0004)/4 = 0x3F */
+
+ struct {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TSV:32;
+ } B;
+ } LDVAL;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TVL:32;
+ } B;
+ } CVAL;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t TIE:1;
+ vuint32_t TEN:1;
+ } B;
+ } TCTRL;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t TIF:1;
+ } B;
+ } TFLG;
+ } CH[8];
+
+ }; /* end of PIT_tag */
+/****************************************************************************/
+/* MODULE : i2c */
+/****************************************************************************/
+ struct I2C_tag {
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t ADR:7;
+ vuint8_t:1;
+ } B;
+ } IBAD; /* Module Bus Address Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t IBC:8;
+ } B;
+ } IBFD; /* Module Bus Frequency Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t MDIS:1;
+ vuint8_t IBIE:1;
+ vuint8_t MS:1;
+ vuint8_t TX:1;
+ vuint8_t NOACK:1;
+ vuint8_t RSTA:1;
+ vuint8_t DMAEN:1;
+ vuint8_t IBDOZE:1;
+ } B;
+ } IBCR; /* Module Bus Control Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t TCF:1;
+ vuint8_t IAAS:1;
+ vuint8_t IBB:1;
+ vuint8_t IBAL:1;
+ vuint8_t:1;
+ vuint8_t SRW:1;
+ vuint8_t IBIF:1;
+ vuint8_t RXAK:1;
+ } B;
+ } IBSR; /* Module Status Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t DATA:8;
+ } B;
+ } IBDR; /* Module Data Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t BIIE:1;
+ vuint8_t:7;
+ } B;
+ } IBIC; /* Module Interrupt Configuration Register */
+
+ }; /* end of I2C_tag */
+/****************************************************************************/
+/* MODULE : MPU */
+/****************************************************************************/
+ struct MPU_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MPERR:8;
+ vuint32_t:4;
+ vuint32_t HRL:4;
+ vuint32_t NSP:4;
+ vuint32_t NGRD:4;
+ vuint32_t:7;
+ vuint32_t VLD:1;
+ } B;
+ } CESR; /* Module Control/Error Status Register */
+
+ uint32_t mpu_reserved1[3]; /* (0x010 - 0x004)/4 = 0x03 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR0;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR0;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR2;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR2;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR3;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR3;
+
+ uint32_t mpu_reserved2[244]; /* (0x0400 - 0x0030)/4 = 0x0F4 */
+
+ struct {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SRTADDR:27;
+ vuint32_t:5;
+ } B;
+ } WORD0; /* Region Descriptor n Word 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ENDADDR:27;
+ vuint32_t:5;
+ } B;
+ } WORD1; /* Region Descriptor n Word 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t M7RE:1;
+ vuint32_t M7WE:1;
+ vuint32_t M6RE:1;
+ vuint32_t M6WE:1;
+ vuint32_t M5RE:1;
+ vuint32_t M5WE:1;
+ vuint32_t M4RE:1;
+ vuint32_t M4WE:1;
+ vuint32_t M3PE:1;
+ vuint32_t M3SM:2;
+ vuint32_t M3UM:3;
+ vuint32_t M2PE:1;
+ vuint32_t M2SM:2;
+ vuint32_t M2UM:3;
+ vuint32_t M1PE:1;
+ vuint32_t M1SM:2;
+ vuint32_t M1UM:3;
+ vuint32_t M0PE:1;
+ vuint32_t M0SM:2;
+ vuint32_t M0UM:3;
+ } B;
+ } WORD2; /* Region Descriptor n Word 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PID:8;
+ vuint32_t PIDMASK:8;
+ vuint32_t:15;
+ vuint32_t VLD:1;
+ } B;
+ } WORD3; /* Region Descriptor n Word 3 */
+
+ } RGD[16];
+
+ uint32_t mpu_reserved3[192]; /* (0x0800 - 0x0500)/4 = 0x0C0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t M7RE:1;
+ vuint32_t M7WE:1;
+ vuint32_t M6RE:1;
+ vuint32_t M6WE:1;
+ vuint32_t M5RE:1;
+ vuint32_t M5WE:1;
+ vuint32_t M4RE:1;
+ vuint32_t M4WE:1;
+ vuint32_t M3PE:1;
+ vuint32_t M3SM:2;
+ vuint32_t M3UM:3;
+ vuint32_t M2PE:1;
+ vuint32_t M2SM:2;
+ vuint32_t M2UM:3;
+ vuint32_t M1PE:1;
+ vuint32_t M1SM:2;
+ vuint32_t M1UM:3;
+ vuint32_t M0PE:1;
+ vuint32_t M0SM:2;
+ vuint32_t M0UM:3;
+ } B;
+ } RGDAAC[16]; /* Region Descriptor Alternate Access Control n */
+
+ }; /* end of MPU_tag */
+/****************************************************************************/
+/* MODULE : eDMA */
+/****************************************************************************/
+
+/*for standard format TCD (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0) */
+ struct EDMA_TCD_STD_tag {
+
+ vuint32_t SADDR; /* source address */
+
+ vuint16_t SMOD:5; /* source address modulo */
+ vuint16_t SSIZE:3; /* source transfer size */
+ vuint16_t DMOD:5; /* destination address modulo */
+ vuint16_t DSIZE:3; /* destination transfer size */
+ vint16_t SOFF; /* signed source address offset */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SMLOE:1;
+ vuint32_t DMLOE:1;
+ int32_t MLOFF:20;
+ vuint32_t NBYTES:10;
+ } B;
+ } NBYTESu; /* Region Descriptor Alternate Access Control n */
+
+ vint32_t SLAST; /* last destination address adjustment, or
+ scatter/gather address (if e_sg = 1) */
+
+ vuint32_t DADDR; /* destination address */
+
+ vuint16_t CITERE_LINK:1;
+ vuint16_t CITER:15;
+
+ vint16_t DOFF; /* signed destination address offset */
+
+ vint32_t DLAST_SGA;
+
+ vuint16_t BITERE_LINK:1; /* beginning major iteration count */
+ vuint16_t BITER:15;
+
+ vuint16_t BWC:2; /* bandwidth control */
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */
+ vuint16_t DONE:1; /* channel done */
+ vuint16_t ACTIVE:1; /* channel active */
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */
+ vuint16_t D_REQ:1; /* disable ipd_req when done */
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */
+ vuint16_t START:1; /* explicit channel start */
+
+ }; /* end of EDMA_TCD_STD_tag */
+
+/*for channel link format TCD (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1)*/
+ struct EDMA_TCD_CHLINK_tag {
+
+ vuint32_t SADDR; /* source address */
+
+ vuint16_t SMOD:5; /* source address modulo */
+ vuint16_t SSIZE:3; /* source transfer size */
+ vuint16_t DMOD:5; /* destination address modulo */
+ vuint16_t DSIZE:3; /* destination transfer size */
+ vint16_t SOFF; /* signed source address offset */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SMLOE:1;
+ vuint32_t DMLOE:1;
+ int32_t MLOFF:20;
+ vuint32_t NBYTES:10;
+ } B;
+ } NBYTESu; /* Region Descriptor Alternate Access Control n */
+ vint32_t SLAST; /* last destination address adjustment, or
+ scatter/gather address (if e_sg = 1) */
+
+ vuint32_t DADDR; /* destination address */
+
+ vuint16_t CITERE_LINK:1;
+ vuint16_t CITERLINKCH:6;
+ vuint16_t CITER:9;
+
+ vint16_t DOFF; /* signed destination address offset */
+
+ vint32_t DLAST_SGA;
+
+ vuint16_t BITERE_LINK:1; /* beginning major iteration count */
+ vuint16_t BITERLINKCH:6;
+ vuint16_t BITER:9;
+
+ vuint16_t BWC:2; /* bandwidth control */
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */
+ vuint16_t DONE:1; /* channel done */
+ vuint16_t ACTIVE:1; /* channel active */
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */
+ vuint16_t D_REQ:1; /* disable ipd_req when done */
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */
+ vuint16_t START:1; /* explicit channel start */
+
+ }; /* end of EDMA_TCD_CHLINK_tag */
+
+ struct EDMA_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t CX:1;
+ vuint32_t ECX:1;
+ vuint32_t GRP3PRI:2;
+ vuint32_t GRP2PRI:2;
+ vuint32_t GRP1PRI:2;
+ vuint32_t GRP0PRI:2;
+ vuint32_t EMLM:1;
+ vuint32_t CLM:1;
+ vuint32_t HALT:1;
+ vuint32_t HOE:1;
+ vuint32_t ERGA:1;
+ vuint32_t ERCA:1;
+ vuint32_t EDBG:1;
+ vuint32_t EBW:1;
+ } B;
+ } CR; /* Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t VLD:1;
+ vuint32_t:15;
+ vuint32_t GPE:1;
+ vuint32_t CPE:1;
+ vuint32_t ERRCHN:6;
+ vuint32_t SAE:1;
+ vuint32_t SOE:1;
+ vuint32_t DAE:1;
+ vuint32_t DOE:1;
+ vuint32_t NCE:1;
+ vuint32_t SGE:1;
+ vuint32_t SBE:1;
+ vuint32_t DBE:1;
+ } B;
+ } ESR; /* Error Status Register */
+
+ int16_t EDMA_reserved1[3]; /* (0x0E - 0x08)/2 = 0x03 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t ERQ15:1;
+ vuint16_t ERQ14:1;
+ vuint16_t ERQ13:1;
+ vuint16_t ERQ12:1;
+ vuint16_t ERQ11:1;
+ vuint16_t ERQ10:1;
+ vuint16_t ERQ09:1;
+ vuint16_t ERQ08:1;
+ vuint16_t ERQ07:1;
+ vuint16_t ERQ06:1;
+ vuint16_t ERQ05:1;
+ vuint16_t ERQ04:1;
+ vuint16_t ERQ03:1;
+ vuint16_t ERQ02:1;
+ vuint16_t ERQ01:1;
+ vuint16_t ERQ00:1;
+ } B;
+ } ERQRL; /* DMA Enable Request Register Low */
+
+ int16_t EDMA_reserved2[3]; /* (0x16 - 0x10)/2 = 0x03 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t EEI15:1;
+ vuint16_t EEI14:1;
+ vuint16_t EEI13:1;
+ vuint16_t EEI12:1;
+ vuint16_t EEI11:1;
+ vuint16_t EEI10:1;
+ vuint16_t EEI09:1;
+ vuint16_t EEI08:1;
+ vuint16_t EEI07:1;
+ vuint16_t EEI06:1;
+ vuint16_t EEI05:1;
+ vuint16_t EEI04:1;
+ vuint16_t EEI03:1;
+ vuint16_t EEI02:1;
+ vuint16_t EEI01:1;
+ vuint16_t EEI00:1;
+ } B;
+ } EEIRL; /* DMA Enable Error Interrupt Register Low */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t SERQ:7;
+ } B;
+ } SERQR; /* DMA Set Enable Request Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CERQ:7;
+ } B;
+ } CERQR; /* DMA Clear Enable Request Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t SEEI:7;
+ } B;
+ } SEEIR; /* DMA Set Enable Error Interrupt Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CEEI:7;
+ } B;
+ } CEEIR; /* DMA Clear Enable Error Interrupt Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CINT:7;
+ } B;
+ } CIRQR; /* DMA Clear Interrupt Request Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CER:7;
+ } B;
+ } CERR; /* DMA Clear error Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t SSB:7;
+ } B;
+ } SSBR; /* Set Start Bit Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CDSB:7;
+ } B;
+ } CDSBR; /* Clear Done Status Bit Register */
+
+ int16_t EDMA_reserved3[3]; /* (0x26 - 0x20)/2 = 0x03 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t INT15:1;
+ vuint16_t INT14:1;
+ vuint16_t INT13:1;
+ vuint16_t INT12:1;
+ vuint16_t INT11:1;
+ vuint16_t INT10:1;
+ vuint16_t INT09:1;
+ vuint16_t INT08:1;
+ vuint16_t INT07:1;
+ vuint16_t INT06:1;
+ vuint16_t INT05:1;
+ vuint16_t INT04:1;
+ vuint16_t INT03:1;
+ vuint16_t INT02:1;
+ vuint16_t INT01:1;
+ vuint16_t INT00:1;
+ } B;
+ } IRQRL; /* DMA Interrupt Request Low */
+
+ int16_t EDMA_reserved4[3]; /* (0x2E - 0x28)/2 = 0x03 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t ERR15:1;
+ vuint16_t ERR14:1;
+ vuint16_t ERR13:1;
+ vuint16_t ERR12:1;
+ vuint16_t ERR11:1;
+ vuint16_t ERR10:1;
+ vuint16_t ERR09:1;
+ vuint16_t ERR08:1;
+ vuint16_t ERR07:1;
+ vuint16_t ERR06:1;
+ vuint16_t ERR05:1;
+ vuint16_t ERR04:1;
+ vuint16_t ERR03:1;
+ vuint16_t ERR02:1;
+ vuint16_t ERR01:1;
+ vuint16_t ERR00:1;
+ } B;
+ } ERL; /* DMA Error Low */
+
+ int16_t EDMA_reserved5[3]; /* (0x36 - 0x30)/2 = 0x03 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t HRS15:1;
+ vuint16_t HRS14:1;
+ vuint16_t HRS13:1;
+ vuint16_t HRS12:1;
+ vuint16_t HRS11:1;
+ vuint16_t HRS10:1;
+ vuint16_t HRS09:1;
+ vuint16_t HRS08:1;
+ vuint16_t HRS07:1;
+ vuint16_t HRS06:1;
+ vuint16_t HRS05:1;
+ vuint16_t HRS04:1;
+ vuint16_t HRS03:1;
+ vuint16_t HRS02:1;
+ vuint16_t HRS01:1;
+ vuint16_t HRS00:1;
+ } B;
+ } HRSL; /* DMA Hardware Request Status Low */
+
+ uint32_t edma_reserved1[50]; /* (0x100 - 0x038)/4 = 0x32 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t ECP:1;
+ vuint8_t DPA:1;
+ vuint8_t GRPPRI:2;
+ vuint8_t CHPRI:4;
+ } B;
+ } CPR[16]; /* Channel n Priority */
+
+ uint32_t edma_reserved2[956]; /* (0x1000 - 0x0110)/4 = 0x3BC */
+
+ struct EDMA_TCD_STD_tag TCD[16];
+ /* struct EDMA_TCD_CHLINK_tag TCD[16]; */
+
+ }; /* end of EDMA_tag */
+/****************************************************************************/
+/* MODULE : INTC */
+/****************************************************************************/
+ struct INTC_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t VTES:1;
+ vuint32_t:4;
+ vuint32_t HVEN:1;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ int32_t INTC_reserved1; /* (0x008 - 0x004)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t PRI:4;
+ } B;
+ } CPR; /* Current Priority Register */
+
+ int32_t INTC_reserved2; /* (0x010 - 0x00C)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t VTBA:21;
+ vuint32_t INTVEC:9;
+ vuint32_t:2;
+ } B;
+ } IACKR; /* Interrupt Acknowledge Register */
+
+ int32_t INTC_reserved3; /* (0x018 - 0x014)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } EOIR; /* End of Interrupt Register */
+
+ int32_t INTC_reserved4; /* (0x020 - 0x01C)/4 = 0x01 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:6;
+ vuint8_t SET:1;
+ vuint8_t CLR:1;
+ } B;
+ } SSCIR[8]; /* Software Set/Clear Interruput Register */
+
+ uint32_t intc_reserved5[6]; /* (0x040 - 0x028)/4 = 0x06 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t PRI:4;
+ } B;
+ } PSR[512]; /* Software Set/Clear Interrupt Register */
+
+ }; /* end of INTC_tag */
+/****************************************************************************/
+/* MODULE : DSPI */
+/****************************************************************************/
+ struct DSPI_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MSTR:1;
+ vuint32_t CONT_SCKE:1;
+ vuint32_t DCONF:2;
+ vuint32_t FRZ:1;
+ vuint32_t MTFE:1;
+ vuint32_t PCSSE:1;
+ vuint32_t ROOE:1;
+ vuint32_t:2;
+ vuint32_t PCSIS5:1;
+ vuint32_t PCSIS4:1;
+ vuint32_t PCSIS3:1;
+ vuint32_t PCSIS2:1;
+ vuint32_t PCSIS1:1;
+ vuint32_t PCSIS0:1;
+ vuint32_t DOZE:1;
+ vuint32_t MDIS:1;
+ vuint32_t DIS_TXF:1;
+ vuint32_t DIS_RXF:1;
+ vuint32_t CLR_TXF:1;
+ vuint32_t CLR_RXF:1;
+ vuint32_t SMPL_PT:2;
+ vuint32_t:7;
+ vuint32_t HALT:1;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ uint32_t dspi_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCNT:16;
+ vuint32_t:16;
+ } B;
+ } TCR;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DBR:1;
+ vuint32_t FMSZ:4;
+ vuint32_t CPOL:1;
+ vuint32_t CPHA:1;
+ vuint32_t LSBFE:1;
+ vuint32_t PCSSCK:2;
+ vuint32_t PASC:2;
+ vuint32_t PDT:2;
+ vuint32_t PBR:2;
+ vuint32_t CSSCK:4;
+ vuint32_t ASC:4;
+ vuint32_t DT:4;
+ vuint32_t BR:4;
+ } B;
+ } CTAR[8]; /* Clock and Transfer Attributes Registers */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCF:1;
+ vuint32_t TXRXS:1;
+ vuint32_t:1;
+ vuint32_t EOQF:1;
+ vuint32_t TFUF:1;
+ vuint32_t:1;
+ vuint32_t TFFF:1;
+ vuint32_t:5;
+ vuint32_t RFOF:1;
+ vuint32_t:1;
+ vuint32_t RFDF:1;
+ vuint32_t:1;
+ vuint32_t TXCTR:4;
+ vuint32_t TXNXTPTR:4;
+ vuint32_t RXCTR:4;
+ vuint32_t POPNXTPTR:4;
+ } B;
+ } SR; /* Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCFRE:1;
+ vuint32_t:2;
+ vuint32_t EOQFRE:1;
+ vuint32_t TFUFRE:1;
+ vuint32_t:1;
+ vuint32_t TFFFRE:1;
+ vuint32_t TFFFDIRS:1;
+ vuint32_t:4;
+ vuint32_t RFOFRE:1;
+ vuint32_t:1;
+ vuint32_t RFDFRE:1;
+ vuint32_t RFDFDIRS:1;
+ vuint32_t:16;
+ } B;
+ } RSER; /* DMA/Interrupt Request Select and Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CONT:1;
+ vuint32_t CTAS:3;
+ vuint32_t EOQ:1;
+ vuint32_t CTCNT:1;
+ vuint32_t:4;
+ vuint32_t PCS5:1;
+ vuint32_t PCS4:1;
+ vuint32_t PCS3:1;
+ vuint32_t PCS2:1;
+ vuint32_t PCS1:1;
+ vuint32_t PCS0:1;
+ vuint32_t TXDATA:16;
+ } B;
+ } PUSHR; /* PUSH TX FIFO Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RXDATA:16;
+ } B;
+ } POPR; /* POP RX FIFO Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TXCMD:16;
+ vuint32_t TXDATA:16;
+ } B;
+ } TXFR[4]; /* Transmit FIFO Registers */
+
+ vuint32_t DSPI_reserved_txf[12];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RXDATA:16;
+ } B;
+ } RXFR[4]; /* Transmit FIFO Registers */
+
+ vuint32_t DSPI_reserved_rxf[12];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MTOE:1;
+ vuint32_t:1;
+ vuint32_t MTOCNT:6;
+ vuint32_t:4;
+ vuint32_t TXSS:1;
+ vuint32_t TPOL:1;
+ vuint32_t TRRE:1;
+ vuint32_t CID:1;
+ vuint32_t DCONT:1;
+ vuint32_t DSICTAS:3;
+ vuint32_t:6;
+ vuint32_t DPCS5:1;
+ vuint32_t DPCS4:1;
+ vuint32_t DPCS3:1;
+ vuint32_t DPCS2:1;
+ vuint32_t DPCS1:1;
+ vuint32_t DPCS0:1;
+ } B;
+ } DSICR; /* DSI Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t SER_DATA:16;
+ } B;
+ } SDR; /* DSI Serialization Data Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t ASER_DATA:16;
+ } B;
+ } ASDR; /* DSI Alternate Serialization Data Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t COMP_DATA:16;
+ } B;
+ } COMPR; /* DSI Transmit Comparison Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DESER_DATA:16;
+ } B;
+ } DDR; /* DSI deserialization Data Register */
+
+ }; /* end of DSPI_tag */
+/****************************************************************************/
+/* MODULE : FlexCAN */
+/****************************************************************************/
+ struct FLEXCAN_BUF_t {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t CODE:4;
+ vuint32_t:1;
+ vuint32_t SRR:1;
+ vuint32_t IDE:1;
+ vuint32_t RTR:1;
+ vuint32_t LENGTH:4;
+ vuint32_t TIMESTAMP:16;
+ } B;
+ } CS;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRIO:3;
+ vuint32_t STD_ID:11;
+ vuint32_t EXT_ID:18;
+ } B;
+ } ID;
+
+ union {
+ /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) */
+ /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */
+ /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */
+ } DATA;
+
+ }; /* end of FLEXCAN_BUF_t */
+
+ struct FLEXCAN_RXFIFO_t {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:9;
+ vuint32_t SRR:1;
+ vuint32_t IDE:1;
+ vuint32_t RTR:1;
+ vuint32_t LENGTH:4;
+ vuint32_t TIMESTAMP:16;
+ } B;
+ } CS;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t STD_ID:11;
+ vuint32_t EXT_ID:18;
+ } B;
+ } ID;
+
+ union {
+ /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) */
+ /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */
+ /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */
+ } DATA;
+
+ uint32_t FLEXCAN_RXFIFO_reserved[20]; /* {0x00E0-0x0090}/0x4 = 0x14 */
+
+ union {
+ vuint32_t R;
+ } IDTABLE[8];
+
+ }; /* end of FLEXCAN_RXFIFO_t */
+
+ struct FLEXCAN_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ vuint32_t FEN:1;
+ vuint32_t HALT:1;
+ vuint32_t NOTRDY:1;
+ vuint32_t WAKMSK:1;
+ vuint32_t SOFTRST:1;
+ vuint32_t FRZACK:1;
+ vuint32_t SUPV:1;
+ vuint32_t SLFWAK:1;
+ vuint32_t WRNEN:1;
+ vuint32_t LPMACK:1;
+ vuint32_t WAKSRC:1;
+ vuint32_t DOZE:1;
+ vuint32_t SRXDIS:1;
+ vuint32_t BCC:1;
+ vuint32_t:2;
+ vuint32_t LPRIO_EN:1;
+ vuint32_t AEN:1;
+ vuint32_t:2;
+ vuint32_t IDAM:2;
+ vuint32_t:2;
+ vuint32_t MAXMB:6;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRESDIV:8;
+ vuint32_t RJW:2;
+ vuint32_t PSEG1:3;
+ vuint32_t PSEG2:3;
+ vuint32_t BOFFMSK:1;
+ vuint32_t ERRMSK:1;
+ vuint32_t CLKSRC:1;
+ vuint32_t LPB:1;
+ vuint32_t TWRNMSK:1;
+ vuint32_t RWRNMSK:1;
+ vuint32_t:2;
+ vuint32_t SMP:1;
+ vuint32_t BOFFREC:1;
+ vuint32_t TSYN:1;
+ vuint32_t LBUF:1;
+ vuint32_t LOM:1;
+ vuint32_t PROPSEG:3;
+ } B;
+ } CR; /* Control Register */
+
+ union {
+ vuint32_t R;
+ } TIMER; /* Free Running Timer */
+
+ uint32_t FLEXCAN_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RXGMASK; /* RX Global Mask */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RX14MASK; /* RX 14 Mask */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RX15MASK; /* RX 15 Mask */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RXECNT:8;
+ vuint32_t TXECNT:8;
+ } B;
+ } ECR; /* Error Counter Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t TWRNINT:1;
+ vuint32_t RWRNINT:1;
+ vuint32_t BIT1ERR:1;
+ vuint32_t BIT0ERR:1;
+ vuint32_t ACKERR:1;
+ vuint32_t CRCERR:1;
+ vuint32_t FRMERR:1;
+ vuint32_t STFERR:1;
+ vuint32_t TXWRN:1;
+ vuint32_t RXWRN:1;
+ vuint32_t IDLE:1;
+ vuint32_t TXRX:1;
+ vuint32_t FLTCONF:2;
+ vuint32_t:1;
+ vuint32_t BOFFINT:1;
+ vuint32_t ERRINT:1;
+ vuint32_t WAKINT:1;
+ } B;
+ } ESR; /* Error and Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF63M:1;
+ vuint32_t BUF62M:1;
+ vuint32_t BUF61M:1;
+ vuint32_t BUF60M:1;
+ vuint32_t BUF59M:1;
+ vuint32_t BUF58M:1;
+ vuint32_t BUF57M:1;
+ vuint32_t BUF56M:1;
+ vuint32_t BUF55M:1;
+ vuint32_t BUF54M:1;
+ vuint32_t BUF53M:1;
+ vuint32_t BUF52M:1;
+ vuint32_t BUF51M:1;
+ vuint32_t BUF50M:1;
+ vuint32_t BUF49M:1;
+ vuint32_t BUF48M:1;
+ vuint32_t BUF47M:1;
+ vuint32_t BUF46M:1;
+ vuint32_t BUF45M:1;
+ vuint32_t BUF44M:1;
+ vuint32_t BUF43M:1;
+ vuint32_t BUF42M:1;
+ vuint32_t BUF41M:1;
+ vuint32_t BUF40M:1;
+ vuint32_t BUF39M:1;
+ vuint32_t BUF38M:1;
+ vuint32_t BUF37M:1;
+ vuint32_t BUF36M:1;
+ vuint32_t BUF35M:1;
+ vuint32_t BUF34M:1;
+ vuint32_t BUF33M:1;
+ vuint32_t BUF32M:1;
+ } B;
+ } IMRH; /* Interruput Masks Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF31M:1;
+ vuint32_t BUF30M:1;
+ vuint32_t BUF29M:1;
+ vuint32_t BUF28M:1;
+ vuint32_t BUF27M:1;
+ vuint32_t BUF26M:1;
+ vuint32_t BUF25M:1;
+ vuint32_t BUF24M:1;
+ vuint32_t BUF23M:1;
+ vuint32_t BUF22M:1;
+ vuint32_t BUF21M:1;
+ vuint32_t BUF20M:1;
+ vuint32_t BUF19M:1;
+ vuint32_t BUF18M:1;
+ vuint32_t BUF17M:1;
+ vuint32_t BUF16M:1;
+ vuint32_t BUF15M:1;
+ vuint32_t BUF14M:1;
+ vuint32_t BUF13M:1;
+ vuint32_t BUF12M:1;
+ vuint32_t BUF11M:1;
+ vuint32_t BUF10M:1;
+ vuint32_t BUF09M:1;
+ vuint32_t BUF08M:1;
+ vuint32_t BUF07M:1;
+ vuint32_t BUF06M:1;
+ vuint32_t BUF05M:1;
+ vuint32_t BUF04M:1;
+ vuint32_t BUF03M:1;
+ vuint32_t BUF02M:1;
+ vuint32_t BUF01M:1;
+ vuint32_t BUF00M:1;
+ } B;
+ } IMRL; /* Interruput Masks Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF63I:1;
+ vuint32_t BUF62I:1;
+ vuint32_t BUF61I:1;
+ vuint32_t BUF60I:1;
+ vuint32_t BUF59I:1;
+ vuint32_t BUF58I:1;
+ vuint32_t BUF57I:1;
+ vuint32_t BUF56I:1;
+ vuint32_t BUF55I:1;
+ vuint32_t BUF54I:1;
+ vuint32_t BUF53I:1;
+ vuint32_t BUF52I:1;
+ vuint32_t BUF51I:1;
+ vuint32_t BUF50I:1;
+ vuint32_t BUF49I:1;
+ vuint32_t BUF48I:1;
+ vuint32_t BUF47I:1;
+ vuint32_t BUF46I:1;
+ vuint32_t BUF45I:1;
+ vuint32_t BUF44I:1;
+ vuint32_t BUF43I:1;
+ vuint32_t BUF42I:1;
+ vuint32_t BUF41I:1;
+ vuint32_t BUF40I:1;
+ vuint32_t BUF39I:1;
+ vuint32_t BUF38I:1;
+ vuint32_t BUF37I:1;
+ vuint32_t BUF36I:1;
+ vuint32_t BUF35I:1;
+ vuint32_t BUF34I:1;
+ vuint32_t BUF33I:1;
+ vuint32_t BUF32I:1;
+ } B;
+ } IFRH; /* Interruput Flag Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF31I:1;
+ vuint32_t BUF30I:1;
+ vuint32_t BUF29I:1;
+ vuint32_t BUF28I:1;
+ vuint32_t BUF27I:1;
+ vuint32_t BUF26I:1;
+ vuint32_t BUF25I:1;
+ vuint32_t BUF24I:1;
+ vuint32_t BUF23I:1;
+ vuint32_t BUF22I:1;
+ vuint32_t BUF21I:1;
+ vuint32_t BUF20I:1;
+ vuint32_t BUF19I:1;
+ vuint32_t BUF18I:1;
+ vuint32_t BUF17I:1;
+ vuint32_t BUF16I:1;
+ vuint32_t BUF15I:1;
+ vuint32_t BUF14I:1;
+ vuint32_t BUF13I:1;
+ vuint32_t BUF12I:1;
+ vuint32_t BUF11I:1;
+ vuint32_t BUF10I:1;
+ vuint32_t BUF09I:1;
+ vuint32_t BUF08I:1;
+ vuint32_t BUF07I:1;
+ vuint32_t BUF06I:1;
+ vuint32_t BUF05I:1;
+ vuint32_t BUF04I:1;
+ vuint32_t BUF03I:1;
+ vuint32_t BUF02I:1;
+ vuint32_t BUF01I:1;
+ vuint32_t BUF00I:1;
+ } B;
+ } IFRL; /* Interrupt Flag Register */
+
+ uint32_t FLEXCAN_reserved2[19]; /* {0x0080-0x0034}/0x4 = 0x13 */
+
+/****************************************************************************/
+/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */
+/****************************************************************************/
+ /* Standard Buffer Structure */
+ struct FLEXCAN_BUF_t BUF[64];
+
+ /* RX FIFO and Buffer Structure */
+ /*struct FLEXCAN_RXFIFO_t RXFIFO; */
+ /*struct FLEXCAN_BUF_t BUF[56]; */
+/****************************************************************************/
+
+ uint32_t FLEXCAN_reserved3[256]; /* {0x0880-0x0480}/0x4 = 0x100 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RXIMR[64]; /* RX Individual Mask Registers */
+
+ }; /* end of FLEXCAN_tag */
+/****************************************************************************/
+/* MODULE : DMAMUX */
+/****************************************************************************/
+ struct DMAMUX_tag {
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t ENBL:1;
+ vuint8_t TRIG:1;
+ vuint8_t SOURCE:6;
+ } B;
+ } CHCONFIG[16]; /* DMA Channel Configuration Register */
+
+ }; /* end of DMAMUX_tag */
+
+/****************************************************************************/
+/* MODULE : DFLASH */
+/****************************************************************************/
+ struct DFLASH_tag {
+ union { /* Module Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t EDC:1;
+ vuint32_t:4;
+ vuint32_t SIZE:3;
+ vuint32_t:1;
+ vuint32_t LAS:3;
+ vuint32_t:3;
+ vuint32_t MAS:1;
+ vuint32_t EER:1;
+ vuint32_t RWE:1;
+ vuint32_t:1;
+ vuint32_t:1;
+ vuint32_t PEAS:1;
+ vuint32_t DONE:1;
+ vuint32_t PEG:1;
+ vuint32_t:4;
+ vuint32_t PGM:1;
+ vuint32_t PSUS:1;
+ vuint32_t ERS:1;
+ vuint32_t ESUS:1;
+ vuint32_t EHV:1;
+ } B;
+ } MCR;
+
+ union { /* LML Register */
+ vuint32_t R;
+ struct {
+ vuint32_t LME:1;
+ vuint32_t:10;
+ vuint32_t TSLK:1;
+ vuint32_t:2;
+ vuint32_t MLK:2;
+ vuint32_t LLK:16;
+ } B;
+ } LML;
+
+ union { /* HBL Register */
+ vuint32_t R;
+ struct {
+ vuint32_t HBE:1;
+ vuint32_t:25;
+ vuint32_t HBLOCK:6;
+ } B;
+ } HBL;
+
+ union { /* SLML Register */
+ vuint32_t R;
+ struct {
+ vuint32_t SLE:1;
+ vuint32_t:10;
+ vuint32_t STSLK:1;
+ vuint32_t:2;
+ vuint32_t SMK:2;
+ vuint32_t SLK:16;
+ } B;
+ } SLL;
+
+ union { /* LMS Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t MSL:2;
+ vuint32_t LSL:16;
+ } B;
+ } LMS;
+
+ union { /* High Address Space Block Select Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t HSL:6;
+ } B;
+ } HBS;
+
+ union { /* Address Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:9;
+ vuint32_t ADD:20;
+ vuint32_t:3;
+ } B;
+ } ADR;
+
+ int32_t Dflash_reserved0[8]; /* {0x003C-0x001C}/0x4 = 0x08 */
+
+ union { /* User Test Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t UTE:1;
+ vuint32_t:7;
+ vuint32_t DSI:8;
+ vuint32_t:10;
+ vuint32_t MRE:1;
+ vuint32_t MRV:1;
+ vuint32_t EIE:1;
+ vuint32_t AIS:1;
+ vuint32_t AIE:1;
+ vuint32_t AID:1;
+ } B;
+ } UT0;
+
+ union { /* User Test Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT1;
+
+ union { /* User Test Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT2;
+
+ union { /* User Multiple Input Signature Register 0-4 */
+ vuint32_t R;
+ struct {
+ vuint32_t MS:32;
+ } B;
+ } UMISR[5];
+
+ }; /* end of Dflash_tag */
+/****************************************************************************/
+/* MODULE : CFLASH */
+/****************************************************************************/
+ struct CFLASH_tag {
+ union { /* Module Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t EDC:1;
+ vuint32_t:4;
+ vuint32_t SIZE:3;
+ vuint32_t:1;
+ vuint32_t LAS:3;
+ vuint32_t:3;
+ vuint32_t MAS:1;
+ vuint32_t EER:1;
+ vuint32_t RWE:1;
+ vuint32_t:1;
+ vuint32_t:1;
+ vuint32_t PEAS:1;
+ vuint32_t DONE:1;
+ vuint32_t PEG:1;
+ vuint32_t:4;
+ vuint32_t PGM:1;
+ vuint32_t PSUS:1;
+ vuint32_t ERS:1;
+ vuint32_t ESUS:1;
+ vuint32_t EHV:1;
+ } B;
+ } MCR;
+
+ union { /* LML Register */
+ vuint32_t R;
+ struct {
+ vuint32_t LME:1;
+ vuint32_t:10;
+ vuint32_t TSLK:1;
+ vuint32_t:2;
+ vuint32_t MLK:2;
+ vuint32_t LLK:16;
+ } B;
+ } LML;
+
+ union { /* HBL Register */
+ vuint32_t R;
+ struct {
+ vuint32_t HBE:1;
+ vuint32_t:19;
+ vuint32_t HBLOCK:12;
+ } B;
+ } HBL;
+
+ union { /* SLML Register */
+ vuint32_t R;
+ struct {
+ vuint32_t SLE:1;
+ vuint32_t:10;
+ vuint32_t STSLK:1;
+ vuint32_t:2;
+ vuint32_t SMK:2;
+ vuint32_t SLK:16;
+ } B;
+ } SLL;
+
+ union { /* LMS Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t MSL:2;
+ vuint32_t LSL:16;
+ } B;
+ } LMS;
+
+ union { /* High Address Space Block Select Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t HSL:12;
+ } B;
+ } HBS;
+
+ union { /* Address Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:9;
+ vuint32_t ADD:20;
+ vuint32_t:3;
+ } B;
+ } ADR;
+
+ union { /* CFLASH Configuration Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t BK0_APC:5;
+ vuint32_t BK0_WWSC:5;
+ vuint32_t BK0_RWSC:5;
+ vuint32_t BK0_RWWC2:1;
+ vuint32_t BK0_RWWC1:1;
+ vuint32_t B0_P1_BCFG:2;
+ vuint32_t B0_P1_DPFE:1;
+ vuint32_t B0_P1_IPFE:1;
+ vuint32_t B0_P1_PFLM:2;
+ vuint32_t B0_P1_BFE:1;
+ vuint32_t BK0_RWWC0:1;
+ vuint32_t B0_P0_BCFG:2;
+ vuint32_t B0_P0_DPFE:1;
+ vuint32_t B0_P0_IPFE:1;
+ vuint32_t B0_P0_PFLM:2;
+ vuint32_t B0_P0_BFE:1;
+ } B;
+ } PFCR0;
+
+ union { /* CFLASH Configuration Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t BK1_APC:5;
+ vuint32_t BK1_WWSC:5;
+ vuint32_t BK1_RWSC:5;
+ vuint32_t BK1_RWWC2:1;
+ vuint32_t BK1_RWWC1:1;
+ vuint32_t:6;
+ vuint32_t B0_P1_BFE:1;
+ vuint32_t BK1_RWWC0:1;
+ vuint32_t:6;
+ vuint32_t B1_P0_BFE:1;
+ } B;
+ } PFCR1;
+
+ union { /* cflash Access Protection Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t ARBM:2;
+ vuint32_t M7PFD:1;
+ vuint32_t M6PFD:1;
+ vuint32_t M5PFD:1;
+ vuint32_t M4PFD:1;
+ vuint32_t M3PFD:1;
+ vuint32_t M2PFD:1;
+ vuint32_t M1PFD:1;
+ vuint32_t M0PFD:1;
+ vuint32_t M7AP:2;
+ vuint32_t M6AP:2;
+ vuint32_t M5AP:2;
+ vuint32_t M4AP:2;
+ vuint32_t M3AP:2;
+ vuint32_t M2AP:2;
+ vuint32_t M1AP:2;
+ vuint32_t M0AP:2;
+ } B;
+ } FAPR;
+
+ int32_t CFLASH_reserved0[5]; /* {0x003C-0x0028}/0x4 = 0x05 */
+
+ union { /* User Test Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t UTE:1;
+ vuint32_t:7;
+ vuint32_t DSI:8;
+ vuint32_t:10;
+ vuint32_t MRE:1;
+ vuint32_t MRV:1;
+ vuint32_t EIE:1;
+ vuint32_t AIS:1;
+ vuint32_t AIE:1;
+ vuint32_t AID:1;
+ } B;
+ } UT0;
+
+ union { /* User Test Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT1;
+
+ union { /* User Test Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT2;
+
+ union { /* User Multiple Input Signature Register 0-4 */
+ vuint32_t R;
+ struct {
+ vuint32_t MS:32;
+ } B;
+ } UMISR[5];
+
+ }; /* end of CFLASH_tag */
+/******************************************************************
+| defines and macros (scope: module-local)
+|-----------------------------------------------------------------*/
+/* Define instances of modules */
+
+#define ADC_0 (*(volatile struct ADC0_tag *) 0xFFE00000UL)
+#define ADC_1 (*(volatile struct ADC1_tag *) 0xFFE04000UL)
+#define CAN_0 (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL)
+#define CAN_1 (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL)
+#define CAN_2 (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL)
+#define CAN_3 (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL)
+#define CAN_4 (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL)
+#define CAN_5 (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL)
+#define CANSP (*(volatile struct CANSP_tag *) 0xFFE70000UL)
+#define CFLASH (*(volatile struct CFLASH_tag *) 0xC3F88000UL)
+#define CGM (*(volatile struct CGM_tag *) 0xC3FE0000UL)
+#define CTUL (*(volatile struct CTUL_tag *) 0xFFE64000UL)
+#define DFLASH (*(volatile struct DFLASH_tag *) 0xC3F8C000UL)
+#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL)
+#define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFF90000UL)
+#define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFF94000UL)
+#define DSPI_2 (*(volatile struct DSPI_tag *) 0xFFF98000UL)
+#define DSPI_3 (*(volatile struct DSPI_tag *) 0xFFF9C000UL)
+#define DSPI_4 (*(volatile struct DSPI_tag *) 0xFFFA0000UL)
+#define DSPI_5 (*(volatile struct DSPI_tag *) 0xFFFA4000UL)
+#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL)
+#define EMIOS_0 (*(volatile struct EMIOS_tag *) 0xC3FA0000UL)
+#define EMIOS_1 (*(volatile struct EMIOS_tag *) 0xC3FA4000UL)
+#define I2C_0 (*(volatile struct I2C_tag *) 0xFFE30000UL)
+#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL)
+#define LINFLEX_0 (*(volatile struct LINFLEX_tag *) 0xFFE40000UL)
+#define LINFLEX_1 (*(volatile struct LINFLEX_tag *) 0xFFE44000UL)
+#define LINFLEX_2 (*(volatile struct LINFLEX_tag *) 0xFFE48000UL)
+#define LINFLEX_3 (*(volatile struct LINFLEX_tag *) 0xFFE4C000UL)
+#define LINFLEX_4 (*(volatile struct LINFLEX_tag *) 0xFFE50000UL)
+#define LINFLEX_5 (*(volatile struct LINFLEX_tag *) 0xFFE54000UL)
+#define LINFLEX_6 (*(volatile struct LINFLEX_tag *) 0xFFE58000UL)
+#define LINFLEX_7 (*(volatile struct LINFLEX_tag *) 0xFFE5C000UL)
+#define LINFLEX_8 (*(volatile struct LINFLEX_tag *) 0xFFFB0000UL)
+#define LINFLEX_9 (*(volatile struct LINFLEX_tag *) 0xFFFB4000UL)
+#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL)
+#define ME (*(volatile struct ME_tag *) 0xC3FDC000UL)
+#define MPU (*(volatile struct MPU_tag *) 0xFFF10000UL)
+#define PCU (*(volatile struct PCU_tag *) 0xC3FE8000UL)
+#define PIT (*(volatile struct PIT_tag *) 0xC3FF0000UL)
+#define RGM (*(volatile struct RGM_tag *) 0xC3FE4000UL)
+#define RTC (*(volatile struct RTC_tag *) 0xC3FEC000UL)
+#define SIU (*(volatile struct SIU_tag *) 0xC3F90000UL)
+#define SSCM (*(volatile struct SSCM_tag *) 0xC3FD8000UL)
+#define STM (*(volatile struct STM_tag *) 0xFFF3C000UL)
+#define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL)
+#define WKUP (*(volatile struct WKUP_tag *) 0xC3F94000UL)
+
+#ifdef __MWERKS__
+#pragma pop
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ifdef _JDP_H */
+/* End of file */
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