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| author | Rocco Marco Guglielmi <roccomarco.guglielmi@live.com> | 2017-08-07 21:41:07 +0000 |
|---|---|---|
| committer | Rocco Marco Guglielmi <roccomarco.guglielmi@live.com> | 2017-08-07 21:41:07 +0000 |
| commit | 53ce03576217052144f2800d0d3634651ef0be01 (patch) | |
| tree | 8559779a85d187f14393f8f042fe7f919488c795 /os/hal/ports/SAMA/SAMA5D2x/hal_lld.h | |
| parent | e1a4894ab6e5161d9734c36daa411ac12efa1f50 (diff) | |
| download | ChibiOS-53ce03576217052144f2800d0d3634651ef0be01.tar.gz ChibiOS-53ce03576217052144f2800d0d3634651ef0be01.tar.bz2 ChibiOS-53ce03576217052144f2800d0d3634651ef0be01.zip | |
Complete clock tree initialization for ATSAMA5D2.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10363 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/SAMA/SAMA5D2x/hal_lld.h')
| -rw-r--r-- | os/hal/ports/SAMA/SAMA5D2x/hal_lld.h | 110 |
1 files changed, 94 insertions, 16 deletions
diff --git a/os/hal/ports/SAMA/SAMA5D2x/hal_lld.h b/os/hal/ports/SAMA/SAMA5D2x/hal_lld.h index 7fb03d864..0a7b8aae5 100644 --- a/os/hal/ports/SAMA/SAMA5D2x/hal_lld.h +++ b/os/hal/ports/SAMA/SAMA5D2x/hal_lld.h @@ -20,6 +20,7 @@ * @pre This module requires the following macros to be defined in the
* @p board.h file:
* - SAMA_MOSCXTCLK.
+ * - SAMA_OSCXTCLK
* .
* One of the following macros must also be defined:
* - SAMA5D21, SAMA5D22, SAMA5D23, SAMA5D24, SAMA5D25, SAMA5D26,
@@ -95,14 +96,14 @@ #define SAMA_PCK_MIN 250000000
/**
- * @brief Maximum processor clock frequency.
+ * @brief Maximum master clock frequency.
*/
-#define SAMA_MCK_MAX 125000000
+#define SAMA_MCK_MAX 166000000
/**
- * @brief Minimum processor clock frequency.
+ * @brief Minimum master clock frequency.
*/
-#define SAMA_MCK_MIN 166000000
+#define SAMA_MCK_MIN 125000000
/**
* @brief Maximum Main Crystal Oscillator clock frequency.
@@ -115,11 +116,6 @@ #define SAMA_MOSCXTCLK_MIN 8000000
/**
- * @brief Crystal 32 clock frequency.
- */
-#define SAMA_OSCXTCLK 32768
-
-/**
* @brief Maximum PLLs input clock frequency.
*/
#define SAMA_PLLIN_MAX 24000000
@@ -242,15 +238,15 @@ /**
* @brief Master clock prescaler.
*/
-#if !defined(SAMA_MCK_PRES) || defined(__DOXYGEN__)
-#define SAMA_MCK_PRES SAMA_MCK_PRE_DIV2
+#if !defined(SAMA_MCK_PRES_VALUE) || defined(__DOXYGEN__)
+#define SAMA_MCK_PRES_VALUE 1
#endif
/**
* @brief Master clock divider.
*/
-#if !defined(SAMA_MCK_MDIV) || defined(__DOXYGEN__)
-#define SAMA_MCK_MDIV SAMA_MCK_MDIV_DIV1
+#if !defined(SAMA_MCK_MDIV_VALUE) || defined(__DOXYGEN__)
+#define SAMA_MCK_MDIV_VALUE 3
#endif
/**
@@ -264,7 +260,7 @@ * @brief PLLADIV2 clock divider.
*/
#if !defined(SAMA_PLLADIV2_EN) || defined(__DOXYGEN__)
-#define SAMA_PLLADIV2_EN FALSE
+#define SAMA_PLLADIV2_EN TRUE
#endif
/** @} */
@@ -280,6 +276,18 @@ #endif
/**
+ * @brief Slow clock value.
+ */
+/* Main oscillator is fed by internal RC. */
+#if (SAMA_OSC_SEL == SAMA_OSC_OSCRC) || defined(__DOXYGEN__)
+#define SAMA_SLOW_CLK SAMA_OSCRCCLK
+#elif (SAMA_OSC_SEL == SAMA_OSC_OSCXT)
+#define SAMA_SLOW_CLK SAMA_OSCXTCLK
+#else
+#error "Wrong SAMA_OSC_SEL value."
+#endif
+
+/**
* @brief MAIN clock value.
*/
/* Main oscillator is fed by internal RC. */
@@ -324,9 +332,9 @@ /**
* @brief PLLA input clock frequency.
- * @todo Condider to add DIVA to this. On SAMA5D27 DIVA is a nonsense since
+ * @todo Consider to add DIVA to this. On SAMA5D27 DIVA is a nonsense since
* it could be only 1 or 0 whereas 0 means PLLA disabled. This could
- * be useful for other chip beloging to this family
+ * be useful for other chip belonging to this family
*/
#define SAMA_PLLACLKIN SAMA_MAIN_CLK
@@ -354,10 +362,80 @@ #define SAMA_PLLADIV 0
#endif
+/**
+ * @brief Master Clock prescaler.
+ */
+#if (SAMA_MCK_PRES_VALUE == 1) || defined(__DOXYGEN__)
+#define SAMA_MCK_PRES SAMA_MCK_PRE_DIV1
+#elif (SAMA_MCK_PRES_VALUE == 2)
+#define SAMA_MCK_PRES SAMA_MCK_PRE_DIV2
+#elif (SAMA_MCK_PRES_VALUE == 4)
+#define SAMA_MCK_PRES SAMA_MCK_PRE_DIV4
+#elif (SAMA_MCK_PRES_VALUE == 8)
+#define SAMA_MCK_PRES SAMA_MCK_PRE_DIV8
+#elif (SAMA_MCK_PRES_VALUE == 16)
+#define SAMA_MCK_PRES SAMA_MCK_PRE_DIV16
+#elif (SAMA_MCK_PRES_VALUE == 32)
+#define SAMA_MCK_PRES SAMA_MCK_PRE_DIV32
+#elif (SAMA_MCK_PRES_VALUE == 64)
+#define SAMA_MCK_PRES SAMA_MCK_PRE_DIV64
+#else
+#error "Wrong SAMA_MCK_PRES_VALUE."
+#endif
+
+/**
+ * @brief Master Clock divider.
+ */
+#if (SAMA_MCK_MDIV_VALUE == 1) || defined(__DOXYGEN__)
+#define SAMA_MCK_MDIV SAMA_MCK_MDIV_DIV1
+#elif (SAMA_MCK_MDIV_VALUE == 2)
+#define SAMA_MCK_MDIV SAMA_MCK_MDIV_DIV2
+#elif (SAMA_MCK_MDIV_VALUE == 3)
+#define SAMA_MCK_MDIV SAMA_MCK_MDIV_DIV3
+#elif (SAMA_MCK_MDIV_VALUE == 4)
+#define SAMA_MCK_MDIV SAMA_MCK_MDIV_DIV4
+#else
+#error "Wrong SAMA_MCK_MDIV_VALUE."
+#endif
+
+/* Check on MDIV and PLLADIV2 value. */
#if (SAMA_MCK_MDIV == SAMA_MCK_MDIV_DIV3) && !SAMA_PLLADIV2_EN
#error "PLLADIV2 must be always enabled when Main Clock Divider is 3"
#endif
+/**
+ * @brief Processor Clock frequency.
+ */
+#if (SAMA_MCK_SEL == SAMA_MCK_SLOW_CLK) || defined(__DOXYGEN__)
+#define SAMA_PCKOUT (SAMA_SLOW_CLK / SAMA_MCK_PRES_VALUE)
+#elif (SAMA_MCK_SEL == SAMA_MCK_MAIN_CLK)
+#define SAMA_PCKOUT (SAMA_MAIN_CLK / SAMA_MCK_PRES_VALUE)
+#elif (SAMA_MCK_SEL == SAMA_MCK_PLLA_CLK)
+#if SAMA_PLLADIV2_EN
+#define SAMA_PCKOUT (SAMA_PLLACLKOUT / SAMA_MCK_PRES_VALUE / 2)
+#else
+#define SAMA_PCKOUT (SAMA_PLLACLKOUT / SAMA_MCK_PRES_VALUE)
+#endif
+#elif (SAMA_MCK_SEL == SAMA_MCK_UPLL_CLK)
+#error "UPLL still unsupported"
+#else
+#error "Wrong SAMA_MCK_SEL."
+#endif
+
+/**
+ * @brief Master Clock frequency.
+ */
+#define SAMA_MCKOUT (SAMA_PCKOUT / SAMA_MCK_MDIV_VALUE)
+
+/* Checks on Processor Clock crystal range. */
+#if (SAMA_PCKOUT > SAMA_PCK_MAX) || (SAMA_PCKOUT < SAMA_PCK_MIN)
+#error "Processor clock frequency out of range."
+#endif
+
+/* Checks on Master Clock crystal range. */
+#if (SAMA_MCKOUT > SAMA_MCK_MAX) || (SAMA_MCKOUT < SAMA_MCK_MIN)
+#error "Master clock frequency out of range."
+#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
|