XDMAC0 is SECURE and XDMAC1 is NOT SECURE

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11499 35acf78f-673a-0410-8e92-d51de3d6d3f4

2 files changed, 76 insertions, 114 deletions

diff --git a/os/hal/ports/SAMA/LLD/DMAv1/sama_xdmac.c b/os/hal/ports/SAMA/LLD/DMAv1/sama_xdmac.c
index d43133307..10793ea40 100644
--- a/os/hal/ports/SAMA/LLD/DMAv1/sama_xdmac.c
+++ b/os/hal/ports/SAMA/LLD/DMAv1/sama_xdmac.c
@@ -38,7 +38,7 @@
 /*===========================================================================*/

 /* Driver exported variables.                                                */

 /*===========================================================================*/

-sama_dma_channel_t _sama_dma_channel_t[XDMAC_CHANNELS_TOT];

+sama_dma_channel_t _sama_dma_channel_t[XDMAC_CHANNELS];

 

 /*===========================================================================*/

 /* Driver local variables and types.                                         */

@@ -53,28 +53,6 @@ sama_dma_channel_t _sama_dma_channel_t[XDMAC_CHANNELS_TOT];
 /*===========================================================================*/

 

 /**

- * @brief   Associates a controller to a DMA channel.

- *

- * @param[in]   index        index of the channel

- * @return      xdmacp       pointer to DMA controller

- *

- * @notapi

- */

-#define dmaControllerSelect(index)                             \

-  index < (XDMAC_CONTROLLERS - 1) ? XDMAC0 : XDMAC1            \

-

-/**

- * @brief   Associates ID number to controller.

- *

- * @param[in]   xdmacp       pointer to DMA controller

- * @return      ID_XDMACx    peripheral ID of DMA controller

- *

- * @notapi

- */

- #define dmaGetControllerId(xdmacp)                            \

-   (Xdmac *) xdmacp == XDMAC0 ? ID_XDMAC0 : ID_XDMAC1

-

-/**

  * @brief   Get content of Global Status register.

  *

  * @param[in]   xdmacp       pointer to DMA controller

@@ -113,54 +91,53 @@ sama_dma_channel_t _sama_dma_channel_t[XDMAC_CHANNELS_TOT];
  * @brief XDMAC interrupt handler

  */

 OSAL_IRQ_HANDLER(dmaHandler) {

-  uint32_t cont;

 

   OSAL_IRQ_PROLOGUE();

-  for (cont = 0; cont < XDMAC_CONTROLLERS; cont++) {

-    uint32_t chan, gis, flags;

-

-    Xdmac *xdmac = dmaControllerSelect(cont);

 

-    /* Read Global Interrupt Status Register */

-    gis = dmaGetGlobalInt(xdmac);

+#if SAMA_HAL_IS_SECURE

+  Xdmac *xdmac = XDMAC0;

+  mtxConfigPeriphSecurity(MATRIX0, ID_XDMAC0, SECURE_PER);

+#else

+  Xdmac *xdmac = XDMAC1;

+#endif /* SAMA_HAL_IS_SECURE */

 

-    if ((gis & 0xFFFF) == 0)

-    /* There is no interrupt pending for this xdmac controller */

-      continue;

+  uint32_t chan, gis, flags;

 

-    for (chan = 0; chan < XDMAC_CHANNELS; chan++) {

-      sama_dma_channel_t *channel = &_sama_dma_channel_t[(cont * XDMAC_CHANNELS) + chan];

-      bool pendingInt = FALSE;

+  /* Read Global Interrupt Status Register */

+  gis = dmaGetGlobalInt(xdmac);

 

-      if (!(gis & (0x1 << chan)))

-      /* There is no pending interrupt for this channel */

-        continue;

+  for (chan = 0; chan < XDMAC_CHANNELS; chan++) {

+    sama_dma_channel_t *channel = &_sama_dma_channel_t[chan];

+    bool pendingInt = FALSE;

 

-      if (channel->state == SAMA_DMA_FREE)

-      /* Channel is free */

-        continue;

+    if (!(gis & (0x1 << chan)))

+    /* There is no pending interrupt for this channel */

+      continue;

 

-      uint32_t cis = dmaGetChannelInt(channel);

+    if (channel->state == SAMA_DMA_FREE)

+    /* Channel is free */

+      continue;

 

-      if (cis & XDMAC_CIS_BIS) {

-        if (!(dmaGetChannelIntMask(channel) & XDMAC_CIM_LIM)) {

-          pendingInt = TRUE;

-        }

-      }

+    uint32_t cis = dmaGetChannelInt(channel);

 

-      if (cis & XDMAC_CIS_LIS) {

+    if (cis & XDMAC_CIS_BIS) {

+      if (!(dmaGetChannelIntMask(channel) & XDMAC_CIM_LIM)) {

         pendingInt = TRUE;

       }

+    }

 

-      if (cis & XDMAC_CIS_DIS) {

-        pendingInt = TRUE;

-      }

-      flags = cis;

+    if (cis & XDMAC_CIS_LIS) {

+      pendingInt = TRUE;

+    }

 

-      /* Execute callback */

-      if (pendingInt && channel->dma_func) {

-        channel->dma_func(channel->dma_param,flags);

-      }

+    if (cis & XDMAC_CIS_DIS) {

+      pendingInt = TRUE;

+    }

+    flags = cis;

+

+    /* Executes callback */

+    if (pendingInt && channel->dma_func) {

+      channel->dma_func(channel->dma_param,flags);

     }

   }

   aicAckInt();

@@ -178,34 +155,34 @@ OSAL_IRQ_HANDLER(dmaHandler) {
  */

 void dmaInit(void) {

 

-  uint8_t cont, chan;

-

 #if SAMA_HAL_IS_SECURE

+  Xdmac *xdmac = XDMAC0;

   mtxConfigPeriphSecurity(MATRIX0, ID_XDMAC0, SECURE_PER);

-  mtxConfigPeriphSecurity(MATRIX0, ID_XDMAC1, SECURE_PER);

+#else

+  Xdmac *xdmac = XDMAC1;

 #endif /* SAMA_HAL_IS_SECURE */

 

-  for (cont = 0; cont < XDMAC_CONTROLLERS; cont++) {

-

-    Xdmac *xdmac = dmaControllerSelect(cont);

-

-    for (chan = 0; chan < XDMAC_CHANNELS; chan++) {

-      sama_dma_channel_t *channel = &_sama_dma_channel_t[(cont * XDMAC_CHANNELS) + chan];

+  uint8_t chan;

 

-      /* Initialization of the specific channel */

-      channel->xdmac    = xdmac;

-      channel->chid     = chan;

-      channel->state    = SAMA_DMA_FREE;

-      channel->dma_func = NULL;

+  for (chan = 0; chan < XDMAC_CHANNELS; chan++) {

+    sama_dma_channel_t *channel = &_sama_dma_channel_t[chan];

 

-      /* Clear interrupts */

-      dmaGetChannelInt(channel);

-    }

+    /* Initialization of the specific channel */

+    channel->xdmac    = xdmac;

+    channel->chid     = chan;

+    channel->state    = SAMA_DMA_FREE;

+    channel->dma_func = NULL;

 

-    uint32_t id = dmaGetControllerId(xdmac);

-    /* set aic source handler */

-    aicSetSourceHandler(id, dmaHandler);

+    /* Clear interrupts */

+    dmaGetChannelInt(channel);

   }

+

+  /* Setting aic source handler */

+#if SAMA_HAL_IS_SECURE

+  aicSetSourceHandler(ID_XDMAC0, dmaHandler);

+#else

+  aicSetSourceHandler(ID_XDMAC1, dmaHandler);

+#endif /* SAMA_HAL_IS_SECURE */

 }

 

 /**

@@ -270,9 +247,8 @@ sama_dma_channel_t* dmaChannelAllocate(uint32_t priority,
                                        void *param) {

 

   sama_dma_channel_t *channel = NULL;

-  uint8_t id;

   uint8_t chan;

-  for (chan = 0; chan < XDMAC_CHANNELS_TOT; chan++) {

+  for (chan = 0; chan < XDMAC_CHANNELS; chan++) {

     channel = &_sama_dma_channel_t[chan];

     if (channel->state != SAMA_DMA_FREE) {

       channel = NULL;

@@ -287,22 +263,20 @@ sama_dma_channel_t* dmaChannelAllocate(uint32_t priority,
     channel->state = SAMA_DMA_NOT_FREE;

     channel->dma_func = func;

     channel->dma_param = param;

-    id = dmaGetControllerId(channel->xdmac);

-

-  /* Setting aic */

-    aicSetSourcePriority(id, priority);

-    aicEnableInt(id);

 

-  /* Enabling DMA clocks required by the current channel set.*/

-    if (id == ID_XDMAC0) {

-      pmcEnableXDMAC0();

-    }

-    else {

-      pmcEnableXDMAC1();

-    }

+  /* Setting AIC and enabling DMA clocks required by the current channel set.*/

+#if SAMA_HAL_IS_SECURE

+  aicSetSourcePriority(ID_XDMAC0, priority);

+  aicEnableInt(ID_XDMAC0);

+  pmcEnableXDMAC0();

+#else

+  aicSetSourcePriority(ID_XDMAC1, priority);

+  aicEnableInt(ID_XDMAC1);

+  pmcEnableXDMAC1();

+#endif /* SAMA_HAL_IS_SECURE */

 

-  /* Enable channel interrupt */

-    channel->xdmac->XDMAC_CHID[channel->chid].XDMAC_CIE =  XDMAC_CIE_BIE;

+  /* Enabling channel's interrupt */

+    channel->xdmac->XDMAC_CHID[channel->chid].XDMAC_CIE = XDMAC_CIE_BIE;

     channel->xdmac->XDMAC_GIE = XDMAC_GIE_IE0 << (channel->chid);

   }

   return channel;

@@ -324,20 +298,22 @@ sama_dma_channel_t* dmaChannelAllocate(uint32_t priority,
 void dmaChannelRelease(sama_dma_channel_t *dmachp) {

 

   osalDbgCheck(dmachp != NULL);

-  uint8_t id;

   /* Check if the channel is free.*/

   osalDbgAssert(dmachp->state != SAMA_DMA_FREE,

                 "not allocated");

-  id = dmaGetControllerId(dmachp->xdmac);

+

+#if SAMA_HAL_IS_SECURE

   /* Disables the associated IRQ vector.*/

-  aicDisableInt(id);

+  aicDisableInt(ID_XDMAC0);

+#else

+  aicDisableInt(ID_XDMAC1);

+#endif /* SAMA_HAL_IS_SECURE */

 

   /* Disables channel */

   dmaChannelDisable(dmachp);

 

   /* Marks the stream as not allocated.*/

   (dmachp)->state = SAMA_DMA_FREE;

-

 }

 

 #endif /* SAMA_DMA_REQUIRED */

diff --git a/os/hal/ports/SAMA/LLD/DMAv1/sama_xdmac.h b/os/hal/ports/SAMA/LLD/DMAv1/sama_xdmac.h
index a3246baf5..84f75f855 100644
--- a/os/hal/ports/SAMA/LLD/DMAv1/sama_xdmac.h
+++ b/os/hal/ports/SAMA/LLD/DMAv1/sama_xdmac.h
@@ -37,24 +37,12 @@
 #define SAMA_XDMAC_ADVANCED         TRUE

 

 /**

- * @brief   Total number of DMA controllers.

- * @details This is the total number of DMA controllers.

- */

-#define XDMAC_CONTROLLERS           2

-

-/**

  * @brief   Number of DMA channels.

  * @details This is the number of DMA channel for each controller.

  */

 #define XDMAC_CHANNELS              (XDMACCHID_NUMBER)

 

 /**

- * @brief   Total number of DMA channels.

- * @details This is the total number of channels among all the DMA units.

- */

-#define XDMAC_CHANNELS_TOT          (XDMACCHID_NUMBER * XDMAC_CONTROLLERS)

-

-/**

  * @brief   Max single transfer size.

  * @details This is the maximum single transfer size supported.

  */

@@ -144,7 +132,7 @@ typedef struct {
  * @{

  */

 /**

- * @brief   Get content of Channel Interrupt Status register.

+ * @brief   Gets content of Channel Interrupt Status register.

  * @note    Reading interrupt is equivalent to clearing interrupt.

  *

  * @param[in] dmachp      pointer to a sama_dma_channel_t structure

@@ -185,8 +173,6 @@ typedef struct {
   (dmachp)->xdmac->XDMAC_CHID[(dmachp)->chid].XDMAC_CDA = XDMAC_CDA_DA((uint32_t)addr); \

 }

 

-

-

 /**

  * @brief   Sets the channel mode settings.

  * @note    This function can be invoked in both ISR or thread context.

@@ -203,7 +189,7 @@ typedef struct {
 }

 

 /**

- * @brief   DMA channel enable.

+ * @brief   Enables DMA channel.

  * @note    This function can be invoked in both ISR or thread context.

  *          The hardware disables a channel on transfer completion by clearing

  *          bit XDMAC_GS.STx.

@@ -290,7 +276,7 @@ typedef struct {
 /*===========================================================================*/

 

 #if !defined(__DOXYGEN__)

-extern sama_dma_channel_t _sama_dma_channel_t[XDMAC_CHANNELS_TOT];

+extern sama_dma_channel_t _sama_dma_channel_t[XDMAC_CHANNELS];

 #endif

 

 #ifdef __cplusplus