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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-02-07 18:57:30 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-02-07 18:57:30 +0000 |
| commit | e3f3b4cd2c8b1af674bf965346426451ae4dee84 (patch) | |
| tree | d76e27cae5c767c00a32b64a37eb84360a4a3722 /os/hal/platforms | |
| parent | 1792e5db26da991d9edbfdd6df88eb89b965a873 (diff) | |
| download | ChibiOS-e3f3b4cd2c8b1af674bf965346426451ae4dee84.tar.gz ChibiOS-e3f3b4cd2c8b1af674bf965346426451ae4dee84.tar.bz2 ChibiOS-e3f3b4cd2c8b1af674bf965346426451ae4dee84.zip | |
Fixed bug 3484942.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3934 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms')
| -rw-r--r-- | os/hal/platforms/STM32F2xx/adc_lld.h | 9 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F2xx/hal_lld.c | 4 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F4xx/adc_lld.h | 9 |
3 files changed, 8 insertions, 14 deletions
diff --git a/os/hal/platforms/STM32F2xx/adc_lld.h b/os/hal/platforms/STM32F2xx/adc_lld.h index 2b4c40b92..737fa05c9 100644 --- a/os/hal/platforms/STM32F2xx/adc_lld.h +++ b/os/hal/platforms/STM32F2xx/adc_lld.h @@ -46,11 +46,8 @@ /**
* @brief Maximum HSE clock frequency.
- * @note This value is arbitrary defined, the current datasheet does not
- * define a maximum value (it is TBD). A value of 36MHz is mentioned
- * but without relationship to VDD ranges.
*/
-#define STM32_ADCCLK_MAX 42000000
+#define STM32_ADCCLK_MAX 30000000
/** @} */
/**
@@ -123,9 +120,9 @@ /**
* @brief ADC common clock divider.
* @note This setting is influenced by the VDDA voltage and other
- * external conditions, please refer to the STM32L15x datasheet
+ * external conditions, please refer to the STM32F2xx datasheet
* for more info.<br>
- * See section 6.3.15 "12-bit ADC characteristics".
+ * See section 5.3.20 "12-bit ADC characteristics".
*/
#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__)
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2
diff --git a/os/hal/platforms/STM32F2xx/hal_lld.c b/os/hal/platforms/STM32F2xx/hal_lld.c index 26beb1cf0..1caa61d89 100644 --- a/os/hal/platforms/STM32F2xx/hal_lld.c +++ b/os/hal/platforms/STM32F2xx/hal_lld.c @@ -19,8 +19,8 @@ */
/**
- * @file STM32F4xx/hal_lld.c
- * @brief STM32F4xx HAL subsystem low level driver source.
+ * @file STM32F2xx/hal_lld.c
+ * @brief STM32F2xx HAL subsystem low level driver source.
*
* @addtogroup HAL
* @{
diff --git a/os/hal/platforms/STM32F4xx/adc_lld.h b/os/hal/platforms/STM32F4xx/adc_lld.h index ad70d3e03..21723bd70 100644 --- a/os/hal/platforms/STM32F4xx/adc_lld.h +++ b/os/hal/platforms/STM32F4xx/adc_lld.h @@ -46,11 +46,8 @@ /**
* @brief Maximum HSE clock frequency.
- * @note This value is arbitrary defined, the current datasheet does not
- * define a maximum value (it is TBD). A value of 36MHz is mentioned
- * but without relationship to VDD ranges.
*/
-#define STM32_ADCCLK_MAX 42000000
+#define STM32_ADCCLK_MAX 36000000
/** @} */
/**
@@ -123,9 +120,9 @@ /**
* @brief ADC common clock divider.
* @note This setting is influenced by the VDDA voltage and other
- * external conditions, please refer to the STM32L15x datasheet
+ * external conditions, please refer to the STM32F4xx datasheet
* for more info.<br>
- * See section 6.3.15 "12-bit ADC characteristics".
+ * See section 5.3.20 "12-bit ADC characteristics".
*/
#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__)
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2
|