git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1927 35acf78f-673a-0410-8e92-d51de3d6d3f4

1 files changed, 3 insertions, 3 deletions

diff --git a/os/hal/platforms/STM32/hal_lld.c b/os/hal/platforms/STM32/hal_lld.c
index 2a22fcd0b..c8d7b1335 100644
--- a/os/hal/platforms/STM32/hal_lld.c
+++ b/os/hal/platforms/STM32/hal_lld.c
@@ -167,20 +167,20 @@ void stm32_clock_init(void) {
 

   /* PLL2 setup, it is only performed if the PLL2 clock is selected as source

      for the PLL clock else it is left disabled.*/

+#if STM32_SW == STM32_SW_PLL

 #if STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2

   RCC->CFGR2 |= STM32_PREDIV2 | STM32_PLL2MUL;

   RCC->CR    |= RCC_CR_PLL2ON;

-  while (!(RCC->CR & RCC_CR_PLLRDY))

+  while (!(RCC->CR & RCC_CR_PLL2RDY))

     ;                           /* Waits until PLL is stable.               */

 #endif

 

   /* PLL setup, it is only performed if the PLL is the selected source of

      the system clock else it is left disabled.*/

-#if STM32_SW == STM32_SW_PLL

   RCC->CFGR2 |= STM32_PREDIV1 | STM32_PREDIV1SRC;

   RCC->CFGR  |= STM32_PLLMUL | STM32_PLLSRC;

   RCC->CR    |= RCC_CR_PLLON;

-  while (!(RCC->CR & RCC_CR_PLL2RDY))

+  while (!(RCC->CR & RCC_CR_PLLRDY))

     ;                           /* Waits until PLL2 is stable.              */

 #endif