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authorbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-12-08 17:14:28 +0000
committerbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-12-08 17:14:28 +0000
commit8cdaeffa2c3b38cd0056e6f5bd09d561fdd6ad7d (patch)
treeba0a78987035d807fbf5de99ca51989d738ba73d /os/hal/platforms
parent456edd448c07e54287844fa262e8ab65eb8737fb (diff)
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STM32. RTCv1. Fexed potential problem with RTC_CRL_RSF bit (bug 3593972).
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4888 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms')
-rw-r--r--os/hal/platforms/STM32/RTCv1/rtc_lld.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.c b/os/hal/platforms/STM32/RTCv1/rtc_lld.c
index a8152dd9b..0fb538c2d 100644
--- a/os/hal/platforms/STM32/RTCv1/rtc_lld.c
+++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.c
@@ -133,7 +133,11 @@ CH_IRQ_HANDLER(RTC_IRQHandler) {
*
* @notapi
*/
-void rtc_lld_init(void){
+void rtc_lld_init(void){
+
+ /* RSF bit must be cleared by software after an APB1 reset or an APB1 clock
+ stop. Otherwise its value will not be actual. */
+ RTC->CRL &= ~RTC_CRL_RSF;
/* Required because access to PRL.*/
rtc_lld_apb1_sync();