diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2009-12-05 14:59:37 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2009-12-05 14:59:37 +0000 |
| commit | 646d8a2376e3d476a3d00edb665770596fb252f6 (patch) | |
| tree | 352fb1378b9e520c036050e666a4afb0aa3e5599 /os/hal/platforms | |
| parent | 2f505cf183ad47f6b25677e864e2f426b28c7f6f (diff) | |
| download | ChibiOS-646d8a2376e3d476a3d00edb665770596fb252f6.tar.gz ChibiOS-646d8a2376e3d476a3d00edb665770596fb252f6.tar.bz2 ChibiOS-646d8a2376e3d476a3d00edb665770596fb252f6.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1376 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms')
| -rw-r--r-- | os/hal/platforms/MSP430/hal_lld.h | 4 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/hal_lld.c | 4 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/hal_lld.h | 44 |
3 files changed, 49 insertions, 3 deletions
diff --git a/os/hal/platforms/MSP430/hal_lld.h b/os/hal/platforms/MSP430/hal_lld.h index 07c5863eb..2795a7edc 100644 --- a/os/hal/platforms/MSP430/hal_lld.h +++ b/os/hal/platforms/MSP430/hal_lld.h @@ -51,6 +51,10 @@ #define MSP430_USE_CLOCK MSP430_CLOCK_SOURCE_XT2CLK
#endif
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
/*
* Calculating the derived clock constants. */
diff --git a/os/hal/platforms/STM32/hal_lld.c b/os/hal/platforms/STM32/hal_lld.c index d25b0f026..b69bbbd9b 100644 --- a/os/hal/platforms/STM32/hal_lld.c +++ b/os/hal/platforms/STM32/hal_lld.c @@ -95,7 +95,7 @@ void hal_lld_init(void) { void stm32_clock_init(void) {
/* HSI setup.*/
- RCC->CR = RCC_CR_HSITRIM_RESET_BITS | RCC_CR_HSION;
+ RCC->CR = 0x00000083; /* Reset value, HSI ON. */
while (!(RCC->CR & RCC_CR_HSIRDY))
; /* Waits until HSI stable. */
/* HSE setup.*/
@@ -103,7 +103,7 @@ void stm32_clock_init(void) { while (!(RCC->CR & RCC_CR_HSERDY))
; /* Waits until HSE stable. */
/* PLL setup.*/
- RCC->CFGR = RCC_CFGR_PLLSRC_HSE_BITS | PLLPREBITS | PLLMULBITS;
+ RCC->CFGR = RCC_CFGR_PLLSRC | PLLPREBITS | PLLMULBITS;
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY))
; /* Waits until PLL stable. */
diff --git a/os/hal/platforms/STM32/hal_lld.h b/os/hal/platforms/STM32/hal_lld.h index a6fdc9661..45f74aff0 100644 --- a/os/hal/platforms/STM32/hal_lld.h +++ b/os/hal/platforms/STM32/hal_lld.h @@ -41,13 +41,55 @@ #include "stm32_dma.h"
/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
+/**
+ * @brief System clock setting.
+ * @note Only 48MHz and 72MHz are currently supported. + */
+#if !defined(STM32_SYSCLK) || defined(__DOXYGEN__)
+#define STM32_SYSCLK 72
+#endif
+
/*===========================================================================*/
-/* Driver constants. */
+/* Derived constants and error checks. */
/*===========================================================================*/
+/*
+ * NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16.
+ */
+#define PLLPRE 1
+#if STM32_SYSCLK == 48
+ #define PLLMUL 6
+#elif STM32_SYSCLK == 72
+ #define PLLMUL 9
+#else
+#error "unsupported STM32_SYSCLK setting"
+#endif
+#define PLLCLK ((HSECLK / PLLPRE) * PLLMUL)
+#define SYSCLK PLLCLK
+#define APB1CLK (SYSCLK / 2)
+#define APB2CLK (SYSCLK / 2)
+#define AHB1CLK (SYSCLK / 1)
+
+/*
+ * Values derived from the clock settings.
+ */
+#define PLLPREBITS ((PLLPRE - 1) << 17)
+#define PLLMULBITS ((PLLMUL - 2) << 18)
+#if STM32_SYSCLK == 48
+ #define USBPREBITS RCC_CFGR_USBPRE
+ #define FLASHBITS 0x00000011
+#elif STM32_SYSCLK == 72
+ #define USBPREBITS 0
+ #define FLASHBITS 0x00000012
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
|