aboutsummaryrefslogtreecommitdiffstats
path: root/os/hal/platforms/STM8L
diff options
context:
space:
mode:
authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2010-11-16 18:39:47 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2010-11-16 18:39:47 +0000
commit354bd66eb083691cab4c2c29b32a836805ac5edc (patch)
treea6cdb1387752aaea3715b7551b24c2aaf3c64be6 /os/hal/platforms/STM8L
parent5962467685985de2d79a85a1fcf8b1961d3d72de (diff)
downloadChibiOS-354bd66eb083691cab4c2c29b32a836805ac5edc.tar.gz
ChibiOS-354bd66eb083691cab4c2c29b32a836805ac5edc.tar.bz2
ChibiOS-354bd66eb083691cab4c2c29b32a836805ac5edc.zip
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2371 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM8L')
-rw-r--r--os/hal/platforms/STM8L/hal_lld.c2
-rw-r--r--os/hal/platforms/STM8L/hal_lld.h18
2 files changed, 15 insertions, 5 deletions
diff --git a/os/hal/platforms/STM8L/hal_lld.c b/os/hal/platforms/STM8L/hal_lld.c
index 2d5014303..72cb830f3 100644
--- a/os/hal/platforms/STM8L/hal_lld.c
+++ b/os/hal/platforms/STM8L/hal_lld.c
@@ -100,7 +100,7 @@ void hal_lld_init(void) {
/* SYSCLK switch to the selected source, not necessary if it is HSI.*/
#if STM8L_SYSCLK_SOURCE != CLK_SYSSEL_HSI
/* Switching clock (manual switch mode).*/
- CLK->SWR = STM8_CLOCK_SOURCE;
+ CLK->SWR = STM8L_SYSCLK_SOURCE;
while ((CLK->SWCR & CLK_SWCR_SWIF) == 0)
;
CLK->SWCR = CLK_SWCR_SWEN;
diff --git a/os/hal/platforms/STM8L/hal_lld.h b/os/hal/platforms/STM8L/hal_lld.h
index 1df041782..2e21988e7 100644
--- a/os/hal/platforms/STM8L/hal_lld.h
+++ b/os/hal/platforms/STM8L/hal_lld.h
@@ -42,9 +42,7 @@
#undef FALSE
#undef TRUE
-
#include "stm8l15x.h"
-
#define FALSE 0
#define TRUE (!FALSE)
@@ -217,7 +215,10 @@
#error "requested LSE clock is not enabled"
#endif
-#if STM8L_NO_CLOCK_INIT
+/**
+ * @brief System clock.
+ */
+#if STM8L_NO_CLOCK_INIT || defined(__DOXYGEN__)
#define SYSCLK (HSICLK / 8)
#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSI
#define SYSCLK (HSICLK / (1 << STM8L_SYSCLK_DIVIDER))
@@ -231,7 +232,10 @@
#error "specified invalid SYSCLK source"
#endif
-#if STM8L_NO_CLOCK_INIT
+/**
+ * @brief RTC clock.
+ */
+#if STM8L_NO_CLOCK_INIT || defined(__DOXYGEN__)
#define RTCCLK 0
#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSI
#define RTCCLK (HSICLK / (1 << STM8L_RTCCLK_DIVIDER))
@@ -245,6 +249,12 @@
#error "specified invalid RTCCLK source"
#endif
+/**
+ * @brief CPU clock.
+ * @details On the STM8L the CPU clock is always equal to the system clock.
+ */
+#define CPUCLK SYSCLK
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/