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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-05-04 09:20:30 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-05-04 09:20:30 +0000 |
| commit | 6dc59bdf42a4342127dfbef2c1284bf544295a78 (patch) | |
| tree | 00507dbd431183a5f030126bf3b48229a6666550 /os/hal/platforms/STM32L1xx | |
| parent | 2a2598ff1b1e696b2b6f0076a419329911edac30 (diff) | |
| download | ChibiOS-6dc59bdf42a4342127dfbef2c1284bf544295a78.tar.gz ChibiOS-6dc59bdf42a4342127dfbef2c1284bf544295a78.tar.bz2 ChibiOS-6dc59bdf42a4342127dfbef2c1284bf544295a78.zip | |
ICU support for STM32 TIM9 unit.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5673 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32L1xx')
| -rw-r--r-- | os/hal/platforms/STM32L1xx/stm32_isr.h | 2 | ||||
| -rw-r--r-- | os/hal/platforms/STM32L1xx/stm32_rcc.h | 27 |
2 files changed, 29 insertions, 0 deletions
diff --git a/os/hal/platforms/STM32L1xx/stm32_isr.h b/os/hal/platforms/STM32L1xx/stm32_isr.h index 034ab2205..d90d28c0b 100644 --- a/os/hal/platforms/STM32L1xx/stm32_isr.h +++ b/os/hal/platforms/STM32L1xx/stm32_isr.h @@ -39,10 +39,12 @@ #define STM32_TIM2_HANDLER TIM2_IRQHandler
#define STM32_TIM3_HANDLER TIM3_IRQHandler
#define STM32_TIM4_HANDLER TIM4_IRQHandler
+#define STM32_TIM9_HANDLER TIM9_IRQHandler
#define STM32_TIM2_NUMBER TIM2_IRQn
#define STM32_TIM3_NUMBER TIM3_IRQn
#define STM32_TIM4_NUMBER TIM4_IRQn
+#define STM32_TIM9_NUMBER TIM9_IRQn
/*
* USART units.
diff --git a/os/hal/platforms/STM32L1xx/stm32_rcc.h b/os/hal/platforms/STM32L1xx/stm32_rcc.h index 5155eb340..5340b9e15 100644 --- a/os/hal/platforms/STM32L1xx/stm32_rcc.h +++ b/os/hal/platforms/STM32L1xx/stm32_rcc.h @@ -452,6 +452,33 @@ * @api
*/
#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
+
+/**
+ * @brief Enables the TIM89peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp)
+
+/**
+ * @brief Disables the TIM9 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM9(lp) rccDisableAPB2(RCC_APB2ENR_TIM9EN, lp)
+
+/**
+ * @brief Resets the TIM8 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST)
/** @} */
/**
|