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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-09-22 14:53:42 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-09-22 14:53:42 +0000 |
| commit | 4a3e3fc01ec6dfb4a710db771bee262d5dc9327e (patch) | |
| tree | e1ff2640c6b25bf93b3d461ff867ce3353a62424 /os/hal/platforms/STM32L1xx/adc_lld.c | |
| parent | 40c7a8982aaef28d6ac7cbbd378708f237711ccf (diff) | |
| download | ChibiOS-4a3e3fc01ec6dfb4a710db771bee262d5dc9327e.tar.gz ChibiOS-4a3e3fc01ec6dfb4a710db771bee262d5dc9327e.tar.bz2 ChibiOS-4a3e3fc01ec6dfb4a710db771bee262d5dc9327e.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3381 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32L1xx/adc_lld.c')
| -rw-r--r-- | os/hal/platforms/STM32L1xx/adc_lld.c | 51 |
1 files changed, 38 insertions, 13 deletions
diff --git a/os/hal/platforms/STM32L1xx/adc_lld.c b/os/hal/platforms/STM32L1xx/adc_lld.c index 9ccb198e4..a2149b6ae 100644 --- a/os/hal/platforms/STM32L1xx/adc_lld.c +++ b/os/hal/platforms/STM32L1xx/adc_lld.c @@ -57,20 +57,20 @@ ADCDriver ADCD1; static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
/* DMA errors handling.*/
-#if defined(STM32_ADC_DMA_ERROR_HOOK)
if ((flags & STM32_DMA_ISR_TEIF) != 0) {
- STM32_ADC_DMA_ERROR_HOOK(spip);
+ /* DMA, this could help only if the DMA tries to access an unmapped
+ address space or violates alignment rules.*/
+ _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
}
-#else
- (void)flags;
-#endif
- if ((flags & STM32_DMA_ISR_HTIF) != 0) {
- /* Half transfer processing.*/
- _adc_isr_half_code(adcp);
- }
- if ((flags & STM32_DMA_ISR_TCIF) != 0) {
- /* Transfer complete processing.*/
- _adc_isr_full_code(adcp);
+ else {
+ if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+ /* Half transfer processing.*/
+ _adc_isr_half_code(adcp);
+ }
+ if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+ /* Transfer complete processing.*/
+ _adc_isr_full_code(adcp);
+ }
}
}
@@ -78,6 +78,29 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { /* Driver interrupt handlers. */
/*===========================================================================*/
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+/**
+ * @brief ADC1 interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(UART5_IRQHandler) {
+ uint32_t sr;
+
+ CH_IRQ_PROLOGUE();
+
+ sr = ADC1->SR;
+ ADC1->SR = 0;
+ if (sr & ADC_SR_OVR) {
+ /* ADC overflow condition, this could happen only if the DMA is unable
+ to read data fast enough.*/
+ _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+#endif
+
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
@@ -145,6 +168,7 @@ void adc_lld_stop(ADCDriver *adcp) { if (adcp->state == ADC_READY) {
#if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp) {
+ ADC1->CR1 = 0;
ADC1->CR2 = 0;
dmaStreamRelease(adcp->dmastp);
rccDisableADC1(FALSE);
@@ -182,7 +206,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) { /* ADC setup.*/
adcp->adc->SR = 0;
- adcp->adc->CR1 = grpp->cr1 | ADC_CR1_SCAN;
+ adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN;
adcp->adc->SMPR1 = grpp->smpr1; /* Writing SMPRx requires ADON=0. */
adcp->adc->SMPR2 = grpp->smpr2;
adcp->adc->SMPR3 = grpp->smpr3;
@@ -211,6 +235,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) { void adc_lld_stop_conversion(ADCDriver *adcp) {
dmaStreamDisable(adcp->dmastp);
+ adcp->adc->CR1 = 0;
adcp->adc->CR2 = 0;
}
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