git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3481 35acf78f-673a-0410-8e92-d51de3d6d3f4

5 files changed, 143 insertions, 44 deletions

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h
index ca46e5287..fc40b51a9 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.h
+++ b/os/hal/platforms/STM32F4xx/hal_lld.h
@@ -40,6 +40,10 @@
 

 #include "stm32f4xx.h"

 

+/* STM32 DMA and RCC helpers.*/

+#include "stm32_dma.h"

+#include "stm32_rcc.h"

+

 /*===========================================================================*/

 /* Driver constants.                                                         */

 /*===========================================================================*/

@@ -58,67 +62,67 @@
 /**

  * @brief   Maximum HSE  clock frequency.

  */

-#define STM32_HSECLK_MAX            26000000

+#define STM32_HSECLK_MAX        26000000

 

 /**

  * @brief   Minimum HSE  clock frequency.

  */

-#define STM32_HSECLK_MIN            1000000

+#define STM32_HSECLK_MIN        1000000

 

 /**

  * @brief   Maximum LSE  clock frequency.

  */

-#define STM32_LSECLK_MAX            1000000

+#define STM32_LSECLK_MAX        1000000

 

 /**

  * @brief   Minimum LSE  clock frequency.

  */

-#define STM32_LSECLK_MIN            1000

+#define STM32_LSECLK_MIN        1000

 

 /**

  * @brief   Maximum PLLs input clock frequency.

  */

-#define STM32_PLLIN_MAX             2000000

+#define STM32_PLLIN_MAX         2000000

 

 /**

  * @brief   Maximum PLLs input clock frequency.

  */

-#define STM32_PLLIN_MIN             950000

+#define STM32_PLLIN_MIN         950000

 

 /**

  * @brief   Maximum PLLs VCO clock frequency.

  */

-#define STM32_PLLVCO_MAX            432000000

+#define STM32_PLLVCO_MAX        432000000

 

 /**

  * @brief   Maximum PLLs VCO clock frequency.

  */

-#define STM32_PLLVCO_MIN            192000000

+#define STM32_PLLVCO_MIN        192000000

 

 /**

  * @brief   Maximum PLL output clock frequency.

  */

-#define STM32_PLLOUT_MAX            168000000

+#define STM32_PLLOUT_MAX        168000000

 

 /**

  * @brief   Maximum PLL output clock frequency.

  */

-#define STM32_PLLOUT_MIN            24000000

+#define STM32_PLLOUT_MIN        24000000

 

 /**

  * @brief   Maximum APB1 clock frequency.

  */

-#define STM32_PCLK1_MAX             42000000

+#define STM32_PCLK1_MAX         42000000

 

 /**

  * @brief   Maximum APB2 clock frequency.

  */

-#define STM32_PCLK2_MAX             84000000

+#define STM32_PCLK2_MAX         84000000

 

 /**

  * @brief   Maximum SPI/I2S clock frequency.

  */

-#define STM32_SPII2S_MAX            37500000

+#define STM32_SPII2S_MAX        37500000

 /** @} */

 

 /**

@@ -245,22 +249,30 @@
  * @name    STM32F4xx capabilities

  * @{

  */

+/* ADC attributes.*/

 #define STM32_HAS_ADC1          TRUE

 #define STM32_HAS_ADC2          TRUE

 #define STM32_HAS_ADC3          TRUE

 

+/* CAN attributes.*/

 #define STM32_HAS_CAN1          TRUE

 #define STM32_HAS_CAN2          TRUE

 

+/* DAC attributes.*/

 #define STM32_HAS_DAC           TRUE

 

+/* DMA attributes.*/

+#define STM32_ADVANCED_DMA      TRUE

 #define STM32_HAS_DMA1          TRUE

 #define STM32_HAS_DMA2          TRUE

 

+/* ETH attributes.*/

 #define STM32_HAS_ETH           TRUE

 

+/* EXTI attributes.*/

 #define STM32_EXTI_NUM_CHANNELS 23

 

+/* GPIO attributes.*/

 #define STM32_HAS_GPIOA         TRUE

 #define STM32_HAS_GPIOB         TRUE

 #define STM32_HAS_GPIOC         TRUE

@@ -271,18 +283,41 @@
 #define STM32_HAS_GPIOH         TRUE

 #define STM32_HAS_GPIOI         TRUE

 

+/* I2C attributes.*/

 #define STM32_HAS_I2C1          TRUE

 #define STM32_HAS_I2C2          TRUE

 #define STM32_HAS_I2C3          TRUE

 

+/* RTC attributes.*/

 #define STM32_HAS_RTC           TRUE

 

+/* SDIO attributes.*/

 #define STM32_HAS_SDIO          TRUE

 

+/* SPI attributes.*/

 #define STM32_HAS_SPI1          TRUE

+#define STM32_SPI1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(2, 0) |            \

+                                 STM32_DMA_STREAM_ID_MSK(2, 2))

+#define STM32_SPI1_RX_DMA_CHN   0x00000303

+#define STM32_SPI1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(2, 3) |            \

+                                 STM32_DMA_STREAM_ID_MSK(2, 5))

+#define STM32_SPI1_TX_DMA_CHN   0x00303000

+

 #define STM32_HAS_SPI2          TRUE

-#define STM32_HAS_SPI3          TRUE

+#define STM32_SPI2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 3))

+#define STM32_SPI2_RX_DMA_CHN   0x00000000

+#define STM32_SPI2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))

+#define STM32_SPI2_TX_DMA_CHN   0x00000000

 

+#define STM32_HAS_SPI3          TRUE

+#define STM32_SPI3_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 0) |            \

+                                 STM32_DMA_STREAM_ID_MSK(1, 2))

+#define STM32_SPI3_RX_DMA_CHN   0x00000000

+#define STM32_SPI3_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5) |            \

+                                 STM32_DMA_STREAM_ID_MSK(1, 7))

+#define STM32_SPI3_TX_DMA_CHN   0x00000000

+

+/* TIM attributes.*/

 #define STM32_HAS_TIM1          TRUE

 #define STM32_HAS_TIM2          TRUE

 #define STM32_HAS_TIM3          TRUE

@@ -301,6 +336,7 @@
 #define STM32_HAS_TIM16         FALSE

 #define STM32_HAS_TIM17         FALSE

 

+/* USART attributes.*/

 #define STM32_HAS_USART1        TRUE

 #define STM32_HAS_USART2        TRUE

 #define STM32_HAS_USART3        TRUE

@@ -308,6 +344,7 @@
 #define STM32_HAS_UART5         TRUE

 #define STM32_HAS_USART6        TRUE

 

+/* USB attributes.*/

 #define STM32_HAS_USB           FALSE

 #define STM32_HAS_OTG1          TRUE

 #define STM32_HAS_OTG2          TRUE

@@ -416,6 +453,10 @@
 /*===========================================================================*/

 

 /**

+ * @name    Configuration options

+ * @{

+ */

+/**

  * @brief   Disables the PWR/RCC initialization in the HAL.

  */

 #if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)

@@ -620,6 +661,7 @@
 #if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__)

 #define STM32_PLLI2SR_VALUE         5

 #endif

+/** @} */

 

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */

@@ -1208,10 +1250,6 @@
 /* External declarations.                                                    */

 /*===========================================================================*/

 

-/* STM32 DMA and RCC helpers.*/

-#include "stm32_dma.h"

-#include "stm32_rcc.h"

-

 #ifdef __cplusplus

 extern "C" {

 #endif

diff --git a/os/hal/platforms/STM32F4xx/platform.mk b/os/hal/platforms/STM32F4xx/platform.mk
index 36d555536..6b7df146b 100644
--- a/os/hal/platforms/STM32F4xx/platform.mk
+++ b/os/hal/platforms/STM32F4xx/platform.mk
@@ -1,6 +1,8 @@
 # List of all the STM32L1xx platform files.

-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/hal_lld.c \

+PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/stm32_dma.c \

+              ${CHIBIOS}/os/hal/platforms/STM32F4xx/hal_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \

+              ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c

 

 # Required include directories

diff --git a/os/hal/platforms/STM32F4xx/stm32_dma.c b/os/hal/platforms/STM32F4xx/stm32_dma.c
index dd5a92afb..d7005b77b 100644
--- a/os/hal/platforms/STM32F4xx/stm32_dma.c
+++ b/os/hal/platforms/STM32F4xx/stm32_dma.c
@@ -484,8 +484,8 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
   /* Putting the stream in a safe state.*/

   dmaStreamDisable(dmastp);

   dmaStreamClearInterrupt(dmastp);

-  dmastp->channel->CR = STM32_DMA_CR_RESET_VALUE;

-  dmastp->channel->FCR = STM32_DMA_FCR_RESET_VALUE;

+  dmastp->stream->CR = STM32_DMA_CR_RESET_VALUE;

+  dmastp->stream->FCR = STM32_DMA_FCR_RESET_VALUE;

 

   /* Enables the associated IRQ vector if a callback is defined.*/

   if (func != NULL)

diff --git a/os/hal/platforms/STM32F4xx/stm32_dma.h b/os/hal/platforms/STM32F4xx/stm32_dma.h
index 9aaadb681..d07a9dbe9 100644
--- a/os/hal/platforms/STM32F4xx/stm32_dma.h
+++ b/os/hal/platforms/STM32F4xx/stm32_dma.h
@@ -47,29 +47,80 @@
 #define STM32_DMA_ISR_MASK          0x3D

 

 /**

+ * @brief   Returns the channel associated to the specified stream.

+ *

+ * @param[in] id        the unique numeric stream identifier

+ * @param[in] c         a stream/channel association word, one channel per

+ *                      nibble

+ * @return              Returns the channel associated to the stream.

+ */

+#define STM32_DMA_GETCHANNEL(id, c) ((c) >> (((id) & 7) * 4))

+

+/**

+ * @brief   Returns an unique numeric identifier for a DMA stream.

+ *

+ * @param[in] dma       the DMA unit number

+ * @param[in] stream    the stream number

+ * @return              An unique numeric stream identifier.

+ */

+#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 8) + (stream))

+

+/**

+ * @brief   Returns a DMA stream identifier mask.

+ *

+ *

+ * @param[in] dma       the DMA unit number

+ * @param[in] stream    the stream number

+ * @return              A DMA stream identifier mask.

+ */

+#define STM32_DMA_STREAM_ID_MSK(dma, stream)                                \

+  (1 << STM32_DMA_STREAM_ID(dma, stream))

+

+/**

+ * @brief   Checks if a DMA stream unique identifier belongs to a mask.

+ * @param[in] id        the stream numeric identifier

+ * @param[in] mask      the stream numeric identifiers mask

+ *

+ * @retval              The check result.

+ * @retval FALSE        id does not belong to the mask.

+ * @retval TRUE         id belongs to the mask.

+ */

+#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))

+

+/**

  * @name    DMA streams identifiers

  * @{

  */

-#define STM32_DMA1_STREAM0          (&_stm32_dma_streams[0])

-#define STM32_DMA1_STREAM1          (&_stm32_dma_streams[1])

-#define STM32_DMA1_STREAM2          (&_stm32_dma_streams[2])

-#define STM32_DMA1_STREAM3          (&_stm32_dma_streams[3])

-#define STM32_DMA1_STREAM4          (&_stm32_dma_streams[4])

-#define STM32_DMA1_STREAM5          (&_stm32_dma_streams[5])

-#define STM32_DMA1_STREAM6          (&_stm32_dma_streams[6])

-#define STM32_DMA1_STREAM7          (&_stm32_dma_streams[7])

-#define STM32_DMA2_STREAM0          (&_stm32_dma_streams[8])

-#define STM32_DMA2_STREAM1          (&_stm32_dma_streams[9])

-#define STM32_DMA2_STREAM2          (&_stm32_dma_streams[10])

-#define STM32_DMA2_STREAM3          (&_stm32_dma_streams[11])

-#define STM32_DMA2_STREAM4          (&_stm32_dma_streams[12])

-#define STM32_DMA2_STREAM5          (&_stm32_dma_streams[13])

-#define STM32_DMA2_STREAM6          (&_stm32_dma_streams[14])

-#define STM32_DMA2_STREAM7          (&_stm32_dma_streams[15])

+/**

+ * @brief   Returns a pointer to a stm32_dma_stream_t structure.

+ *

+ * @param[in] id        the stream numeric identifier

+ * @return              A pointer to the stm32_dma_stream_t constant structure

+ *                      associated to the DMA stream.

+ */

+#define STM32_DMA_STREAM(id)        (&_stm32_dma_streams[id])

+

+#define STM32_DMA1_STREAM0          STM32_DMA_STREAM(0)

+#define STM32_DMA1_STREAM1          STM32_DMA_STREAM(1)

+#define STM32_DMA1_STREAM2          STM32_DMA_STREAM(2)

+#define STM32_DMA1_STREAM3          STM32_DMA_STREAM(3)

+#define STM32_DMA1_STREAM4          STM32_DMA_STREAM(4)

+#define STM32_DMA1_STREAM5          STM32_DMA_STREAM(5)

+#define STM32_DMA1_STREAM6          STM32_DMA_STREAM(6)

+#define STM32_DMA1_STREAM7          STM32_DMA_STREAM(7)

+#define STM32_DMA2_STREAM0          STM32_DMA_STREAM(8)

+#define STM32_DMA2_STREAM1          STM32_DMA_STREAM(9)

+#define STM32_DMA2_STREAM2          STM32_DMA_STREAM(10)

+#define STM32_DMA2_STREAM3          STM32_DMA_STREAM(11)

+#define STM32_DMA2_STREAM4          STM32_DMA_STREAM(12)

+#define STM32_DMA2_STREAM5          STM32_DMA_STREAM(13)

+#define STM32_DMA2_STREAM6          STM32_DMA_STREAM(14)

+#define STM32_DMA2_STREAM7          STM32_DMA_STREAM(15)

 /** @} */

 

 /**

  * @name    CR register constants common to all DMA types

+ * @{

  */

 #define STM32_DMA_CR_EN             DMA_SxCR_EN

 #define STM32_DMA_CR_TEIE           DMA_SxCR_TEIE

@@ -90,12 +141,15 @@
 #define STM32_DMA_CR_MSIZE_BYTE     0

 #define STM32_DMA_CR_MSIZE_HWORD    DMA_SxCR_MSIZE_0

 #define STM32_DMA_CR_MSIZE_WORD     DMA_SxCR_MSIZE_1

+#define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_MSIZE_MASK |              \

+                                     STM32_DMA_CR_MSIZE_MASK)

 #define STM32_DMA_CR_PL_MASK        DMA_SxCR_PL

 #define STM32_DMA_CR_PL(n)          ((n) << 16)

 /** @} */

 

 /**

  * @name    CR register constants only found in STM32F2xx/STM32F4xx

+ * @{

  */

 #define STM32_DMA_CR_DMEIE          DMA_SxCR_DMEIE

 #define STM32_DMA_CR_PFCTRL         DMA_SxCR_PFCTRL

@@ -118,6 +172,7 @@
 

 /**

  * @name    FCR register constants only found in STM32F2xx

+ * @{

  */

 #define STM32_DMA_FCR_FEIE          DMA_SxFCR_FEIE

 #define STM32_DMA_FCR_FS_MASK       DMA_SxFCR_FS

@@ -177,6 +232,10 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
 /*===========================================================================*/

 

 /**

+ * @name    Macro Functions

+ * @{

+ */

+/**

  * @brief   Associates a peripheral data register to a DMA stream.

  * @note    This function can be invoked in both ISR or thread context.

  * @pre     The stream must have been allocated using @p dmaStreamAllocate().

@@ -357,6 +416,7 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
 #define dmaWaitCompletion(dmastp)                                           \

   while (((dmastp)->stream->CNDTR > 0) &&                                   \

          ((dmastp)->stream->CCR & STM32_DMA_CR_EN))

+/** @} */

 

 /*===========================================================================*/

 /* External declarations.                                                    */

diff --git a/os/hal/platforms/STM32F4xx/stm32_rcc.h b/os/hal/platforms/STM32F4xx/stm32_rcc.h
index 3a10e57b2..4971a71c5 100644
--- a/os/hal/platforms/STM32F4xx/stm32_rcc.h
+++ b/os/hal/platforms/STM32F4xx/stm32_rcc.h
@@ -27,7 +27,6 @@
  * @addtogroup STM32F4xx_RCC

  * @{

  */

-

 #ifndef _STM32_RCC_

 #define _STM32_RCC_

 

@@ -347,7 +346,7 @@
  *

  * @api

  */

-#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHB1ENR_DMA1EN, lp)

+#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp)

 

 /**

  * @brief   Disables the DMA1 peripheral clock.

@@ -356,14 +355,14 @@
  *

  * @api

  */

-#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHB1ENR_DMA1EN, lp)

+#define rccDisableDMA1(lp) rccDisableAHB1(RCC_AHB1ENR_DMA1EN, lp)

 

 /**

  * @brief   Resets the DMA1 peripheral.

  *

  * @api

  */

-#define rccResetDMA1() rccResetAHB(RCC_AHB1RSTR_DMA1RST)

+#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST)

 

 /**

  * @brief   Enables the DMA2 peripheral clock.

@@ -372,7 +371,7 @@
  *

  * @api

  */

-#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHB1ENR_DMA2EN, lp)

+#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp)

 

 /**

  * @brief   Disables the DMA2 peripheral clock.

@@ -381,14 +380,14 @@
  *

  * @api

  */

-#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHB1ENR_DMA2EN, lp)

+#define rccDisableDMA2(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2EN, lp)

 

 /**

  * @brief   Resets the DMA2 peripheral.

  *

  * @api

  */

-#define rccResetDMA2() rccResetAHB(RCC_AHB1RSTR_DMA2RST)

+#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)

 /** @} */

 

 /**