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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-01-15 09:37:27 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-01-15 09:37:27 +0000
commite2448aac991fff9bc29d892de9d78c6d1714e81c (patch)
treec94f67e6557e95a5eee47684ada870e89b0c05cb /os/hal/platforms/STM32F4xx
parent17f9264b099705e80822be875a0dbc0658ad05fd (diff)
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3811 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F4xx')
-rw-r--r--os/hal/platforms/STM32F4xx/hal_lld.c2
-rw-r--r--os/hal/platforms/STM32F4xx/stm32_dma.h5
2 files changed, 6 insertions, 1 deletions
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 9fbd34b08..d25431f76 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -50,7 +50,7 @@ static void hal_lld_backup_domain_init(void) {
PWR->CR |= PWR_CR_DBP;
/* Reset BKP domain if different clock source selected.*/
- if ((RCC->BDCR & STM32_RTCSEL_MSK) != STM32_RTCSEL){
+ if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0;
diff --git a/os/hal/platforms/STM32F4xx/stm32_dma.h b/os/hal/platforms/STM32F4xx/stm32_dma.h
index bcadf153c..5c0430e7d 100644
--- a/os/hal/platforms/STM32F4xx/stm32_dma.h
+++ b/os/hal/platforms/STM32F4xx/stm32_dma.h
@@ -352,6 +352,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
/**
* @brief DMA stream disable.
+ * @details The function disables the specified stream, waits for the disable
+ * operation to complete and then clears any pending interrupt.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
@@ -362,6 +364,9 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
*/
#define dmaStreamDisable(dmastp) { \
(dmastp)->stream->CR &= ~STM32_DMA_CR_EN; \
+ while (((dmastp)->stream->CR & STM32_DMA_CR_EN) != 0) \
+ ; \
+ dmaStreamClearInterrupt(dmastp); \
}
/**