diff options
author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-11-16 18:55:34 +0000 |
---|---|---|
committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-11-16 18:55:34 +0000 |
commit | cef04f5f4b8ea66ad3ab5a628a4aad8da509039e (patch) | |
tree | 4b5e4f8b06c5703f1c0c61db560c76e7ea975352 /os/hal/platforms/STM32F4xx | |
parent | 0435bb5b4e1435924490f4a268dba5f75e998951 (diff) | |
download | ChibiOS-cef04f5f4b8ea66ad3ab5a628a4aad8da509039e.tar.gz ChibiOS-cef04f5f4b8ea66ad3ab5a628a4aad8da509039e.tar.bz2 ChibiOS-cef04f5f4b8ea66ad3ab5a628a4aad8da509039e.zip |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3500 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F4xx')
-rw-r--r-- | os/hal/platforms/STM32F4xx/adc_lld.c | 31 | ||||
-rw-r--r-- | os/hal/platforms/STM32F4xx/adc_lld.h | 2 |
2 files changed, 27 insertions, 6 deletions
diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c index f78c7ac0f..f34c4fd61 100644 --- a/os/hal/platforms/STM32F4xx/adc_lld.c +++ b/os/hal/platforms/STM32F4xx/adc_lld.c @@ -321,17 +321,16 @@ void adc_lld_start_conversion(ADCDriver *adcp) { /* ADC setup.*/
adcp->adc->SR = 0;
adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN;
- adcp->adc->SMPR1 = grpp->smpr1; /* Writing SMPRx requires ADON=0. */
- adcp->adc->SMPR2 = grpp->smpr2;
adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT | ADC_CR2_DMA | ADC_CR2_DDS |
ADC_CR2_ADON;
+ adcp->adc->SMPR1 = grpp->smpr1;
+ adcp->adc->SMPR2 = grpp->smpr2;
adcp->adc->SQR1 = grpp->sqr1;
adcp->adc->SQR2 = grpp->sqr2;
adcp->adc->SQR3 = grpp->sqr3;
- /* Must wait the ADC to be ready for conversion, see 9.3.6 "Timing diagram"
- in the Reference Manual.*/
- while ((adcp->adc->SR & ADC_SR_ADONS) == 0)
- ;
+ /* TODO: According to section 10.3.6 of the reference manual there should
+ be a 2uS delay between the ADC activation and conversion start.*/
+
/* ADC start by raising ADC_CR2_SWSTART.*/
adcp->adc->CR2 = grpp->cr2 | ADC_CR2_SWSTART | ADC_CR2_CONT | ADC_CR2_DMA |
ADC_CR2_DDS | ADC_CR2_ADON;
@@ -373,6 +372,26 @@ void adcSTM32DisableTSVREFE(void) { ADC->CCR &= ~ADC_CCR_TSVREFE;
}
+/**
+ * @brief Enables the VBATE bit.
+ * @details The VBATE bit is required in order to sample the VBAT channel.
+ * @note This is an STM32-only functionality.
+ */
+void adcSTM32EnableVBATE(void) {
+
+ ADC->CCR |= ADC_CCR_VBATE;
+}
+
+/**
+ * @brief Disables the VBATE bit.
+ * @details The VBATE bit is required in order to sample the VBAT channel.
+ * @note This is an STM32-only functionality.
+ */
+void adcSTM32DisableVBATE(void) {
+
+ ADC->CCR &= ~ADC_CCR_VBATE;
+}
+
#endif /* HAL_USE_ADC */
/** @} */
diff --git a/os/hal/platforms/STM32F4xx/adc_lld.h b/os/hal/platforms/STM32F4xx/adc_lld.h index 0e846f50a..6260773a2 100644 --- a/os/hal/platforms/STM32F4xx/adc_lld.h +++ b/os/hal/platforms/STM32F4xx/adc_lld.h @@ -556,6 +556,8 @@ extern "C" { void adc_lld_stop_conversion(ADCDriver *adcp);
void adcSTM32EnableTSVREFE(void);
void adcSTM32DisableTSVREFE(void);
+ void adcSTM32EnableVBATE(void);
+ void adcSTM32DisableVBATE(void);
#ifdef __cplusplus
}
#endif
|