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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-01-10 18:14:24 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-01-10 18:14:24 +0000 |
| commit | 8824a54e5efd1cc239bd7af2f8cbe12481d7a247 (patch) | |
| tree | 3c052d2d1906dab386e56aa438bc6308bb21ef37 /os/hal/platforms/STM32F4xx | |
| parent | a40e2315db35340bdc80f9b922acbdfeb97be83f (diff) | |
| download | ChibiOS-8824a54e5efd1cc239bd7af2f8cbe12481d7a247.tar.gz ChibiOS-8824a54e5efd1cc239bd7af2f8cbe12481d7a247.tar.bz2 ChibiOS-8824a54e5efd1cc239bd7af2f8cbe12481d7a247.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3783 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F4xx')
| -rw-r--r-- | os/hal/platforms/STM32F4xx/hal_lld.c | 48 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F4xx/hal_lld.h | 22 |
2 files changed, 63 insertions, 7 deletions
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c index 02905b6bd..a655231cd 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.c +++ b/os/hal/platforms/STM32F4xx/hal_lld.c @@ -41,6 +41,47 @@ /* Driver local functions. */
/*===========================================================================*/
+/**
+ * @brief Initializes the backup domain.
+ */
+static void hal_lld_backup_domain_init(void) {
+
+ /* Backup domain access enabled during initialization.*/
+ PWR->CR |= PWR_CR_DBP;
+
+ /* RTC clock initialization.*/
+#if STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
+ /* RTC clock not required, backup domain reset as initialization.*/
+ RCC->BDCR = RCC_BDCR_BDRST;
+ RCC->BDCR = 0;
+#else /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
+ /* If the backup domain hasn't been initialized yet then proceed with
+ initialization.*/
+ if (!(RCC->BDCR & RCC_BDCR_LSEON)) {
+ /* Backup domain reset.*/
+ RCC->BDCR = RCC_BDCR_BDRST;
+ RCC->BDCR = 0;
+
+ /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+ RCC->BDCR |= RCC_BDCR_LSEON;
+ while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+ ; /* Waits until LSE is stable. */
+#endif
+
+ /* Selects clock source.*/
+ RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTCSEL;
+
+ /* RTC enabled regardless its previous status, this will also prevent
+ successive initializations.*/
+ RCC->BDCR |= RCC_BDCR_RTCEN;
+ }
+#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
+
+ /* Backup domain access disabled for operations safety.*/
+ PWR->CR &= ~PWR_CR_DBP;
+}
+
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
@@ -74,13 +115,18 @@ void hal_lld_init(void) { /* DWT cycle counter enable.*/
DWT_CTRL |= DWT_CTRL_CYCCNTENA;
+ /* PWR clock enabled.*/
+ rccEnablePWRInterface(FALSE);
+
+ /* Initializes the backup domain.*/
+ hal_lld_backup_domain_init();
+
#if defined(STM32_DMA_REQUIRED)
dmaInit();
#endif
/* Programmable voltage detector enable.*/
#if STM32_PVD_ENABLE
- rccEnablePWRInterface(FALSE);
PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
#endif /* STM32_PVD_ENABLE */
}
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index 1e5d4947b..2837939a6 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -1250,21 +1250,21 @@ #endif
/**
- * @brief HSE divider toward RTC clock.
+ * @brief RTC HSE divider setting.
*/
-#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
+#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
defined(__DOXYGEN__)
-#define STM32_HSEDIVCLK (STM32_HSECLK / STM32_RTCPRE_VALUE)
+#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16)
#else
#error "invalid STM32_RTCPRE value specified"
#endif
/**
- * @brief RTC HSE divider setting.
+ * @brief HSE divider toward RTC clock.
*/
-#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
+#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
defined(__DOXYGEN__)
-#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16)
+#define STM32_HSEDIVCLK (STM32_HSECLK / STM32_RTCPRE_VALUE)
#else
#error "invalid STM32_RTCPRE value specified"
#endif
@@ -1285,6 +1285,16 @@ #endif
/**
+ * @brief RTC HSE divider setting.
+ */
+#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
+ defined(__DOXYGEN__)
+#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16)
+#else
+#error "invalid STM32_RTCPRE value specified"
+#endif
+
+/**
* @brief 48MHz frequency.
*/
#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__)
|