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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-10-23 20:51:36 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-10-23 20:51:36 +0000
commit7112dfa32e35f35998bf4ab05888317ef5aed59a (patch)
treee67e397e60dafc1f68437b0dba03eb5c2828120e /os/hal/platforms/STM32F4xx
parentefbd7db9789c18e465750646d51a5fab936c5fc6 (diff)
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4777 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F4xx')
-rw-r--r--os/hal/platforms/STM32F4xx/hal_lld.c13
1 files changed, 9 insertions, 4 deletions
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index a1d3d3d79..e3cf144e1 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -26,6 +26,8 @@
* @{
*/
+/* TODO: LSEBYP like in F3.*/
+
#include "ch.h"
#include "hal.h"
@@ -155,12 +157,14 @@ void stm32_clock_init(void) {
; /* Waits until HSI is stable. */
#if STM32_HSE_ENABLED
+ /* HSE activation.*/
#if defined(STM32_HSE_BYPASS)
/* HSE Bypass.*/
- RCC->CR |= RCC_CR_HSEBYP;
-#endif
- /* HSE activation.*/
+ RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
+#else
+ /* No HSE Bypass.*/
RCC->CR |= RCC_CR_HSEON;
+#endif
while ((RCC->CR & RCC_CR_HSERDY) == 0)
; /* Waits until HSE is stable. */
#endif
@@ -185,7 +189,8 @@ void stm32_clock_init(void) {
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
- RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN | STM32_PLLM;
+ RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN |
+ STM32_PLLM;
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY))
; /* Waits until PLL is stable. */