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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-12-22 12:38:21 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-12-22 12:38:21 +0000 |
| commit | da9678f49a11241924c18902f7169c818a3cf995 (patch) | |
| tree | 9968624e8c93b3f9bd5cd869c16c719ed1eda8b0 /os/hal/platforms/STM32F4xx/hal_lld.h | |
| parent | 3d37f49059ee718a3d71e164883373a8cb30d6d8 (diff) | |
| download | ChibiOS-da9678f49a11241924c18902f7169c818a3cf995.tar.gz ChibiOS-da9678f49a11241924c18902f7169c818a3cf995.tar.bz2 ChibiOS-da9678f49a11241924c18902f7169c818a3cf995.zip | |
Provisional STM32F2xx support.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3649 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F4xx/hal_lld.h')
| -rw-r--r-- | os/hal/platforms/STM32F4xx/hal_lld.h | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index dc158b536..3edc87851 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -56,24 +56,24 @@ * @{
*/
/**
- * @brief Maximum HSE clock frequency.
+ * @brief Maximum HSE clock frequency.
*/
#define STM32_HSECLK_MAX 26000000
/**
- * @brief Minimum HSE clock frequency.
+ * @brief Minimum HSE clock frequency.
*/
#define STM32_HSECLK_MIN 1000000
/**
- * @brief Maximum LSE clock frequency.
+ * @brief Maximum LSE clock frequency.
*/
#define STM32_LSECLK_MAX 1000000
/**
- * @brief Minimum LSE clock frequency.
+ * @brief Minimum LSE clock frequency.
*/
-#define STM32_LSECLK_MIN 1000
+#define STM32_LSECLK_MIN 32768
/**
* @brief Maximum PLLs input clock frequency.
@@ -126,7 +126,7 @@ * @{
*/
#define STM32_HSICLK 16000000 /**< High speed internal clock. */
-#define STM32_LSICLK 38000 /**< Low speed internal clock. */
+#define STM32_LSICLK 32000 /**< Low speed internal clock. */
/** @} */
/**
@@ -204,9 +204,9 @@ #define STM32_MCO1SEL_HSE (2 << 21) /**< HSE clock on MCO1 pin. */
#define STM32_MCO1SEL_PLL (3 << 21) /**< PLL clock on MCO1 pin. */
-#define STM32_I2CSRC_MASK (1 << 23) /**< I2CSRC mask. */
-#define STM32_I2CSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */
-#define STM32_I2CSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */
+#define STM32_I2SSRC_MASK (1 << 23) /**< I2CSRC mask. */
+#define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */
+#define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */
#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */
#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */
@@ -732,7 +732,7 @@ * @brief I2S clock source.
*/
#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__)
-#define STM32_I2SSRC STM32_I2CSRC_CKIN
+#define STM32_I2SSRC STM32_I2SSRC_CKIN
#endif
/**
@@ -836,7 +836,7 @@ #error "HSI not enabled, required by STM32_MCO2SEL"
#endif
-#if (STM32_I2SSRC == STM32_I2CSRC_PLLI2S) && \
+#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \
(STM32_PLLSRC == STM32_PLLSRC_HSI)
#error "HSI not enabled, required by STM32_I2SSRC"
#endif
@@ -876,7 +876,7 @@ #error "HSE not enabled, required by STM32_MCO2SEL"
#endif
-#if (STM32_I2SSRC == STM32_I2CSRC_PLLI2S) && \
+#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \
(STM32_PLLSRC == STM32_PLLSRC_HSE)
#error "HSE not enabled, required by STM32_I2SSRC"
#endif
@@ -1126,7 +1126,7 @@ /*
* PLLI2S enable check.
*/
-#if (STM32_I2CSRC == STM32_I2CSRC_PLLI2S) || defined(__DOXYGEN__)
+#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || defined(__DOXYGEN__)
/**
* @brief PLL activation flag.
*/
|