STM32F2xx deleted and merged with STM32F4xx code.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4775 35acf78f-673a-0410-8e92-d51de3d6d3f4

1 files changed, 150 insertions, 15 deletions

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h
index 2f2df3f3c..13ccb41b1 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.h
+++ b/os/hal/platforms/STM32F4xx/hal_lld.h
@@ -20,7 +20,7 @@
 

 /**

  * @file    STM32F4xx/hal_lld.h

- * @brief   STM32F4xx HAL subsystem low level driver header.

+ * @brief   STM32F4xx/STM32F2xx HAL subsystem low level driver header.

  * @pre     This module requires the following macros to be defined in the

  *          @p board.h file:

  *          - STM32_LSECLK.

@@ -29,6 +29,7 @@
  *          - STM32_VDD (as hundredths of Volt).

  *          .

  *          One of the following macros must also be defined:

+ *          - STM32F2XX for High-performance STM32 F-2 devices.

  *          - STM32F4XX for High-performance STM32 F-4 devices.

  *          .

  *

@@ -54,13 +55,18 @@
  * @name    Platform identification

  * @{

  */

-#define PLATFORM_NAME           "STM32F4 High Performance & DSP"

+#if defined(STM32F4XX) || defined(__DOXYGEN__)

+#define PLATFORM_NAME           "STM32F4 High Performance"

+#else /* !defined(STM32F4XX) */

+#define PLATFORM_NAME           "STM32F2 High Performance"

+#endif /* !defined(STM32F4XX) */

 /** @} */

 

 /**

  * @name    Absolute Maximum Ratings

  * @{

  */

+#if defined(STM32F4XX) || defined(__DOXYGEN__)

 /**

  * @brief   Maximum HSE clock frequency.

  */

@@ -125,6 +131,23 @@
  * @brief   Maximum SPI/I2S clock frequency.

  */

 #define STM32_SPII2S_MAX        37500000

+

+#else /* !defined(STM32F4XX) */

+#define STM32_SYSCLK_MAX        120000000

+#define STM32_HSECLK_MAX        26000000

+#define STM32_HSECLK_MIN        1000000

+#define STM32_LSECLK_MAX        1000000

+#define STM32_LSECLK_MIN        32768

+#define STM32_PLLIN_MAX         2000000

+#define STM32_PLLIN_MIN         950000

+#define STM32_PLLVCO_MAX        432000000

+#define STM32_PLLVCO_MIN        192000000

+#define STM32_PLLOUT_MAX        120000000

+#define STM32_PLLOUT_MIN        24000000

+#define STM32_PCLK1_MAX         30000000

+#define STM32_PCLK2_MAX         60000000

+#define STM32_SPII2S_MAX        37500000

+#endif /* !defined(STM32F4XX) */

 /** @} */

 

 /**

@@ -139,10 +162,11 @@
  * @name    PWR_CR register bits definitions

  * @{

  */

+#if defined(STM32F4XX) || defined(__DOXYGEN__)

 #define STM32_VOS_MASK          (1 << 14)   /**< Core voltage mask.         */

 #define STM32_VOS_LOW           (0 << 14)   /**< Core voltage set to low.   */

 #define STM32_VOS_HIGH          (1 << 14)   /**< Core voltage set to high.  */

-

+#endif

 #define STM32_PLS_MASK          (7 << 5)    /**< PLS bits mask.             */

 #define STM32_PLS_LEV0          (0 << 5)    /**< PVD level 0.               */

 #define STM32_PLS_LEV1          (1 << 5)    /**< PVD level 1.               */

@@ -337,7 +361,11 @@
 

 /* RTC attributes.*/

 #define STM32_HAS_RTC           TRUE

+#if defined(STM32F4XX) || defined(__DOXYGEN__)

 #define STM32_RTC_HAS_SUBSECONDS TRUE

+#else

+#define STM32_RTC_HAS_SUBSECONDS FALSE

+#endif

 #define STM32_RTC_IS_CALENDAR   TRUE

 

 /* SDIO attributes.*/

@@ -532,7 +560,9 @@
 #define DCMI_IRQHandler         Vector178   /**< DCMI.                      */ 

 #define CRYP_IRQHandler         Vector17C   /**< CRYP.                      */ 

 #define HASH_RNG_IRQHandler     Vector180   /**< Hash and Rng.              */ 

+#if defined(STM32F4XX) || defined(__DOXYGEN__)

 #define FPU_IRQHandler          Vector184   /**< Floating Point Unit.       */

+#endif

 /** @} */

 

 /*===========================================================================*/

@@ -551,16 +581,6 @@
 #endif

 

 /**

- * @brief   Core voltage selection.

- * @note    This setting affects all the performance and clock related

- *          settings, the maximum performance is only obtainable selecting

- *          the maximum voltage.

- */

-#if !defined(STM32_VOS) || defined(__DOXYGEN__)

-#define STM32_VOS                   STM32_VOS_HIGH

-#endif

-

-/**

  * @brief   Enables or disables the programmable voltage detector.

  */

 #if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)

@@ -620,6 +640,17 @@
 #define STM32_SW                    STM32_SW_PLL

 #endif

 

+#if defined(STM32F4XX) || defined(__DOXYGEN__)

+/**

+ * @brief   Core voltage selection.

+ * @note    This setting affects all the performance and clock related

+ *          settings, the maximum performance is only obtainable selecting

+ *          the maximum voltage.

+ */

+#if !defined(STM32_VOS) || defined(__DOXYGEN__)

+#define STM32_VOS                   STM32_VOS_HIGH

+#endif

+

 /**

  * @brief   Clock source for the PLLs.

  * @note    This setting has only effect if the PLL is selected as the

@@ -671,11 +702,62 @@
 #define STM32_PLLQ_VALUE            7

 #endif

 

+#else /* !defined(STM32F4XX) */

 /**

- * @brief   AHB prescaler value.

- * @note    The default value is calculated for a 168MHz system clock from

+ * @brief   Clock source for the PLLs.

+ * @note    This setting has only effect if the PLL is selected as the

+ *          system clock source.

+ * @note    The default value is calculated for a 120MHz system clock from

  *          an external 8MHz HSE clock.

  */

+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)

+#define STM32_PLLSRC                STM32_PLLSRC_HSE

+#endif

+

+/**

+ * @brief   PLLM divider value.

+ * @note    The allowed values are 2..63.

+ * @note    The default value is calculated for a 120MHz system clock from

+ *          an external 8MHz HSE clock.

+ */

+#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)

+#define STM32_PLLM_VALUE            8

+#endif

+

+/**

+ * @brief   PLLN multiplier value.

+ * @note    The allowed values are 192..432.

+ * @note    The default value is calculated for a 120MHz system clock from

+ *          an external 8MHz HSE clock.

+ */

+#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)

+#define STM32_PLLN_VALUE            240

+#endif

+

+/**

+ * @brief   PLLP divider value.

+ * @note    The allowed values are 2, 4, 6, 8.

+ * @note    The default value is calculated for a 120MHz system clock from

+ *          an external 8MHz HSE clock.

+ */

+#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)

+#define STM32_PLLP_VALUE            2

+#endif

+

+/**

+ * @brief   PLLQ multiplier value.

+ * @note    The allowed values are 2..15.

+ * @note    The default value is calculated for a 120MHz system clock from

+ *          an external 8MHz HSE clock.

+ */

+#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)

+#define STM32_PLLQ_VALUE            5

+#endif

+#endif /* !defined(STM32F4XX) */

+

+/**

+ * @brief   AHB prescaler value.

+ */

 #if !defined(STM32_HPRE) || defined(__DOXYGEN__)

 #define STM32_HPRE                  STM32_HPRE_DIV1

 #endif

@@ -768,6 +850,7 @@
 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

+#if defined(STM32F4XX) || defined(__DOXYGEN__)

 /*

  * Configuration-related checks.

  */

@@ -785,10 +868,20 @@
 #define STM32_SYSCLK_MAX            144000000

 #endif

 

+#else /* !defined(STM32F4XX) */

+/*

+ * Configuration-related checks.

+ */

+#if !defined(STM32F2xx_MCUCONF)

+#error "Using a wrong mcuconf.h file, STM32F2xx_MCUCONF not defined"

+#endif

+#endif /* !defined(STM32F4XX) */

+

 /**

  * @brief   Maximum frequency thresholds and wait states for flash access.

  * @note    The values are valid for 2.7V to 3.6V supply range.

  */

+#if defined(STM32F4XX) || defined(__DOXYGEN__)

 #if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__)

 #define STM32_0WS_THRESHOLD         30000000

 #define STM32_1WS_THRESHOLD         60000000

@@ -829,6 +922,48 @@
 #error "invalid VDD voltage specified"

 #endif

 

+#else /* !defined(STM32F4XX) */

+#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__)

+#define STM32_0WS_THRESHOLD         30000000

+#define STM32_1WS_THRESHOLD         60000000

+#define STM32_2WS_THRESHOLD         90000000

+#define STM32_3WS_THRESHOLD         120000000

+#define STM32_4WS_THRESHOLD         0

+#define STM32_5WS_THRESHOLD         0

+#define STM32_6WS_THRESHOLD         0

+#define STM32_7WS_THRESHOLD         0

+#elif (STM32_VDD >= 240) && (STM32_VDD < 270)

+#define STM32_0WS_THRESHOLD         24000000

+#define STM32_1WS_THRESHOLD         48000000

+#define STM32_2WS_THRESHOLD         72000000

+#define STM32_3WS_THRESHOLD         96000000

+#define STM32_4WS_THRESHOLD         120000000

+#define STM32_5WS_THRESHOLD         0

+#define STM32_6WS_THRESHOLD         0

+#define STM32_7WS_THRESHOLD         0

+#elif (STM32_VDD >= 210) && (STM32_VDD < 240)

+#define STM32_0WS_THRESHOLD         18000000

+#define STM32_1WS_THRESHOLD         36000000

+#define STM32_2WS_THRESHOLD         54000000

+#define STM32_3WS_THRESHOLD         72000000

+#define STM32_4WS_THRESHOLD         90000000

+#define STM32_5WS_THRESHOLD         108000000

+#define STM32_6WS_THRESHOLD         120000000

+#define STM32_7WS_THRESHOLD         0

+#elif (STM32_VDD >= 180) && (STM32_VDD < 210)

+#define STM32_0WS_THRESHOLD         16000000

+#define STM32_1WS_THRESHOLD         32000000

+#define STM32_2WS_THRESHOLD         48000000

+#define STM32_3WS_THRESHOLD         64000000

+#define STM32_4WS_THRESHOLD         80000000

+#define STM32_5WS_THRESHOLD         96000000

+#define STM32_6WS_THRESHOLD         112000000

+#define STM32_7WS_THRESHOLD         120000000

+#else

+#error "invalid VDD voltage specified"

+#endif

+#endif /* !defined(STM32F4XX) */

+

 /*

  * HSI related checks.

  */