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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-12-05 14:15:57 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-12-05 14:15:57 +0000 |
| commit | 3e27095da10bcf997c71d32d1af59aa99f3804c4 (patch) | |
| tree | 31263ed5719be4d3f5f270502af5e1db932c5b19 /os/hal/platforms/STM32F3xx | |
| parent | d501fe85d1816bd8fc20cd8354f7b339df9ecc27 (diff) | |
| download | ChibiOS-3e27095da10bcf997c71d32d1af59aa99f3804c4.tar.gz ChibiOS-3e27095da10bcf997c71d32d1af59aa99f3804c4.tar.bz2 ChibiOS-3e27095da10bcf997c71d32d1af59aa99f3804c4.zip | |
SPI for STM32F3xx, not working yet.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4875 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F3xx')
| -rw-r--r-- | os/hal/platforms/STM32F3xx/hal_lld.h | 2 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F3xx/stm32_rcc.h | 27 |
2 files changed, 28 insertions, 1 deletions
diff --git a/os/hal/platforms/STM32F3xx/hal_lld.h b/os/hal/platforms/STM32F3xx/hal_lld.h index 1830cc542..348bba45c 100644 --- a/os/hal/platforms/STM32F3xx/hal_lld.h +++ b/os/hal/platforms/STM32F3xx/hal_lld.h @@ -567,7 +567,7 @@ * @brief APB2 prescaler value.
*/
#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
-#define STM32_PPRE2 STM32_PPRE2_DIV1
+#define STM32_PPRE2 STM32_PPRE2_DIV2
#endif
/**
diff --git a/os/hal/platforms/STM32F3xx/stm32_rcc.h b/os/hal/platforms/STM32F3xx/stm32_rcc.h index 460d1c351..229333104 100644 --- a/os/hal/platforms/STM32F3xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F3xx/stm32_rcc.h @@ -389,6 +389,33 @@ * @api
*/
#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
+
+/**
+ * @brief Enables the SPI3 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp)
+
+/**
+ * @brief Disables the SPI3 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp)
+
+/**
+ * @brief Resets the SPI3 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST)
/** @} */
/**
|