git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3430 35acf78f-673a-0410-8e92-d51de3d6d3f4

3 files changed, 869 insertions, 2 deletions

diff --git a/os/hal/platforms/STM32F2xx/platform.mk b/os/hal/platforms/STM32F2xx/platform.mk
index c1502009f..64365e897 100644
--- a/os/hal/platforms/STM32F2xx/platform.mk
+++ b/os/hal/platforms/STM32F2xx/platform.mk
@@ -9,5 +9,4 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F2xx/hal_lld.c \
 # Required include directories

 PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F2xx \

               ${CHIBIOS}/os/hal/platforms/STM32 \

-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \

-              ${CHIBIOS}/os/hal/platforms/STM32/DMAv2

+              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2

diff --git a/os/hal/platforms/STM32F2xx/stm32_dma.c b/os/hal/platforms/STM32F2xx/stm32_dma.c
new file mode 100644
index 000000000..70f412083
--- /dev/null
+++ b/os/hal/platforms/STM32F2xx/stm32_dma.c
@@ -0,0 +1,541 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,

+                 2011 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    DMAv2/stm32_dma.c

+ * @brief   Enhanced DMA helper driver code.

+ *

+ * @addtogroup STM32_DMA

+ * @details DMA sharing helper driver. In the STM32 the DMA streams are a

+ *          shared resource, this driver allows to allocate and free DMA

+ *          streams at runtime in order to allow all the other device

+ *          drivers to coordinate the access to the resource.

+ * @note    The DMA ISR handlers are all declared into this module because

+ *          sharing, the various device drivers can associate a callback to

+ *          IRSs when allocating streams.

+ * @{

+ */

+

+#include "ch.h"

+#include "hal.h"

+

+/* The following macro is only defined if some driver requiring DMA services

+   has been enabled.*/

+#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)

+

+/*===========================================================================*/

+/* Driver local definitions.                                                 */

+/*===========================================================================*/

+

+/**

+ * @brief   Mask of the DMA1 streams in @p dma_streams_mask.

+ */

+#define STM32_DMA1_STREAMS_MASK     0x000000FF

+

+/**

+ * @brief   Mask of the DMA2 streams in @p dma_streams_mask.

+ */

+#define STM32_DMA2_STREAMS_MASK     0x0000FF00

+

+/**

+ * @brief   Post-reset value of the stream CR register.

+ */

+#define STM32_DMA_CR_RESET_VALUE    0x00000000

+

+/**

+ * @brief   Post-reset value of the stream FCR register.

+ */

+#define STM32_DMA_FCR_RESET_VALUE   0x00000021

+

+/*===========================================================================*/

+/* Driver exported variables.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   DMA streams descriptors.

+ * @details This table keeps the association between an unique stream

+ *          identifier and the involved physical registers.

+ * @note    Don't use this array directly, use the appropriate wrapper macros

+ *          instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc.

+ */

+const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {

+  {0, DMA1, DMA1_Stream0, &DMA1->LIFCR, 0},

+  {1, DMA1, DMA1_Stream1, &DMA1->LIFCR, 6},

+  {2, DMA1, DMA1_Stream2, &DMA1->LIFCR, 16},

+  {3, DMA1, DMA1_Stream3, &DMA1->LIFCR, 22},

+  {4, DMA1, DMA1_Stream4, &DMA1->HIFCR, 0},

+  {5, DMA1, DMA1_Stream5, &DMA1->HIFCR, 6},

+  {6, DMA1, DMA1_Stream6, &DMA1->HIFCR, 16},

+  {7, DMA1, DMA1_Stream7, &DMA1->HIFCR, 22},

+  {8, DMA2, DMA2_Stream0, &DMA2->LIFCR, 0},

+  {9, DMA2, DMA2_Stream1, &DMA2->LIFCR, 6},

+  {10, DMA2, DMA2_Stream2, &DMA2->LIFCR, 16},

+  {11, DMA2, DMA2_Stream3, &DMA2->LIFCR, 22},

+  {12, DMA2, DMA2_Stream4, &DMA2->HIFCR, 0},

+  {13, DMA2, DMA2_Stream5, &DMA2->HIFCR, 6},

+  {14, DMA2, DMA2_Stream6, &DMA2->HIFCR, 16},

+  {15, DMA2, DMA2_Stream7, &DMA2->HIFCR, 22},

+};

+

+/*===========================================================================*/

+/* Driver local variables and types.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   DMA ISR redirector type.

+ */

+typedef struct {

+  stm32_dmaisr_t        dma_func;

+  void                  *dma_param;

+} dma_isr_redir_t;

+

+/**

+ * @brief   Mask of the allocated streams.

+ */

+static uint32_t dma_streams_mask;

+

+/**

+ * @brief   DMA IRQ redirectors.

+ */

+static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];

+

+/*===========================================================================*/

+/* Driver local functions.                                                   */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver interrupt handlers.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   DMA1 stream 0 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA1_Stream0_IRQHandler) {

+  uint32_t flags;

+

+  CH_IRQ_PROLOGUE();

+

+  flags = (DMA1->LISR >> 0) & STM32_DMA_ISR_MASK;

+  DMA1->LIFCR = STM32_DMA_ISR_MASK << 0;

+  if (dma_isr_redir[0].dma_func)

+    dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA1 stream 1 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA1_Stream1_IRQHandler) {

+  uint32_t flags;

+

+  CH_IRQ_PROLOGUE();

+

+  flags = (DMA1->LISR >> 6) & STM32_DMA_ISR_MASK;

+  DMA1->LIFCR = STM32_DMA_ISR_MASK << 6;

+  if (dma_isr_redir[1].dma_func)

+    dma_isr_redir[1].dma_func(dma_isr_redir[0].dma_param, flags);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA1 stream 2 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA1_Stream2_IRQHandler) {

+  uint32_t flags;

+

+  CH_IRQ_PROLOGUE();

+

+  flags = (DMA1->LISR >> 16) & STM32_DMA_ISR_MASK;

+  DMA1->LIFCR = STM32_DMA_ISR_MASK << 16;

+  if (dma_isr_redir[2].dma_func)

+    dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA1 stream 3 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA1_Stream3_IRQHandler) {

+  uint32_t flags;

+

+  CH_IRQ_PROLOGUE();

+

+  flags = (DMA1->LISR >> 22) & STM32_DMA_ISR_MASK;

+  DMA1->LIFCR = STM32_DMA_ISR_MASK << 22;

+  if (dma_isr_redir[3].dma_func)

+    dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA1 stream 4 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA1_Stream4_IRQHandler) {

+  uint32_t flags;

+

+  CH_IRQ_PROLOGUE();

+

+  flags = (DMA1->HISR >> 0) & STM32_DMA_ISR_MASK;

+  DMA1->HIFCR = STM32_DMA_ISR_MASK << 0;

+  if (dma_isr_redir[4].dma_func)

+    dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA1 stream 5 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA1_Stream5_IRQHandler) {

+  uint32_t flags;

+

+  CH_IRQ_PROLOGUE();

+

+  flags = (DMA1->HISR >> 6) & STM32_DMA_ISR_MASK;

+  DMA1->HIFCR = STM32_DMA_ISR_MASK << 6;

+  if (dma_isr_redir[5].dma_func)

+    dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA1 stream 6 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA1_Stream6_IRQHandler) {

+  uint32_t flags;

+

+  CH_IRQ_PROLOGUE();

+

+  flags = (DMA1->HISR >> 16) & STM32_DMA_ISR_MASK;

+  DMA1->HIFCR = STM32_DMA_ISR_MASK << 16;

+  if (dma_isr_redir[6].dma_func)

+    dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA1 stream 7 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA1_Stream7_IRQHandler) {

+  uint32_t flags;

+

+  CH_IRQ_PROLOGUE();

+

+  flags = (DMA1->HISR >> 22) & STM32_DMA_ISR_MASK;

+  DMA1->HIFCR = STM32_DMA_ISR_MASK << 22;

+  if (dma_isr_redir[7].dma_func)

+    dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA2 stream 0 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA2_Stream0_IRQHandler) {

+  uint32_t flags;

+

+  CH_IRQ_PROLOGUE();

+

+  flags = (DMA2->LISR >> 0) & STM32_DMA_ISR_MASK;

+  DMA2->LIFCR = STM32_DMA_ISR_MASK << 0;

+  if (dma_isr_redir[8].dma_func)

+    dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA2 stream 1 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA2_Stream1_IRQHandler) {

+  uint32_t flags;

+

+  CH_IRQ_PROLOGUE();

+

+  flags = (DMA2->LISR >> 6) & STM32_DMA_ISR_MASK;

+  DMA2->LIFCR = STM32_DMA_ISR_MASK << 6;

+  if (dma_isr_redir[9].dma_func)

+    dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA2 stream 2 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA2_Stream2_IRQHandler) {

+  uint32_t flags;

+

+  CH_IRQ_PROLOGUE();

+

+  flags = (DMA2->LISR >> 16) & STM32_DMA_ISR_MASK;

+  DMA2->LIFCR = STM32_DMA_ISR_MASK << 16;

+  if (dma_isr_redir[10].dma_func)

+    dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA2 stream 3 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA2_Stream3_IRQHandler) {

+  uint32_t flags;

+

+  CH_IRQ_PROLOGUE();

+

+  flags = (DMA2->LISR >> 22) & STM32_DMA_ISR_MASK;

+  DMA2->LIFCR = STM32_DMA_ISR_MASK << 22;

+  if (dma_isr_redir[11].dma_func)

+    dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA2 stream 4 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA2_Stream4_IRQHandler) {

+  uint32_t flags;

+

+  CH_IRQ_PROLOGUE();

+

+  flags = (DMA2->HISR >> 0) & STM32_DMA_ISR_MASK;

+  DMA2->HIFCR = STM32_DMA_ISR_MASK << 0;

+  if (dma_isr_redir[12].dma_func)

+    dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA2 stream 5 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA2_Stream5_IRQHandler) {

+  uint32_t flags;

+

+  CH_IRQ_PROLOGUE();

+

+  flags = (DMA2->HISR >> 6) & STM32_DMA_ISR_MASK;

+  DMA2->HIFCR = STM32_DMA_ISR_MASK << 6;

+  if (dma_isr_redir[13].dma_func)

+    dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA2 stream 6 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA2_Stream6_IRQHandler) {

+  uint32_t flags;

+

+  CH_IRQ_PROLOGUE();

+

+  flags = (DMA2->HISR >> 16) & STM32_DMA_ISR_MASK;

+  DMA2->HIFCR = STM32_DMA_ISR_MASK << 16;

+  if (dma_isr_redir[14].dma_func)

+    dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   DMA2 stream 7 shared interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(DMA2_Stream7_IRQHandler) {

+  uint32_t flags;

+

+  CH_IRQ_PROLOGUE();

+

+  flags = (DMA2->HISR >> 22) & STM32_DMA_ISR_MASK;

+  DMA2->HIFCR = STM32_DMA_ISR_MASK << 22;

+  if (dma_isr_redir[15].dma_func)

+    dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags);

+

+  CH_IRQ_EPILOGUE();

+}

+

+/*===========================================================================*/

+/* Driver exported functions.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   STM32 DMA helper initialization.

+ *

+ * @init

+ */

+void dmaInit(void) {

+  int i;

+

+  dma_streams_mask = 0;

+  for (i = 0; i < STM32_DMA_STREAMS; i++) {

+    _stm32_dma_streams[i].stream->CR = 0;

+    dma_isr_redir[i].dma_func = NULL;

+  }

+  DMA1->LIFCR = 0xFFFFFFFF;

+  DMA1->HIFCR = 0xFFFFFFFF;

+  DMA2->LIFCR = 0xFFFFFFFF;

+  DMA2->HIFCR = 0xFFFFFFFF;

+}

+

+/**

+ * @brief   Allocates a DMA stream.

+ * @details The stream is allocated and, if required, the DMA clock enabled.

+ *          The function also enables the IRQ vector associated to the stream

+ *          and initializes its priority.

+ * @pre     The stream must not be already in use or an error is returned.

+ * @post    The stream is allocated and the default ISR handler redirected

+ *          to the specified function.

+ * @post    The stream ISR vector is enabled and its priority configured.

+ * @post    The stream must be freed using @p dmaStreamRelease() before it can

+ *          be reused with another peripheral.

+ * @post    The stream is in its post-reset state.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

+ * @param[in] priority  IRQ priority mask for the DMA stream

+ * @param[in] func      handling function pointer, can be @p NULL

+ * @param[in] param     a parameter to be passed to the handling function

+ * @return              The operation status.

+ * @retval FALSE        no error, stream taken.

+ * @retval TRUE         error, stream already taken.

+ *

+ * @special

+ */

+bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,

+                         uint32_t priority,

+                         stm32_dmaisr_t func,

+                         void *param) {

+

+  chDbgCheck(dmastp != NULL, "dmaAllocate");

+

+  /* Checks if the stream is already taken.*/

+  if ((dma_streams_mask & dmastp->mask) != 0)

+    return TRUE;

+

+  /* Marks the stream as allocated.*/

+  dma_isr_redir[dmastp->selfindex].dma_func  = func;

+  dma_isr_redir[dmastp->selfindex].dma_param = param;

+  dma_streams_mask |= (1 << dmastp->selfindex);

+

+  /* Enabling DMA clocks required by the current streams set.*/

+  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0) {

+    RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;

+    RCC->AHB1LPENR |= RCC_AHB1LPENR_DMA1LPEN;

+  }

+  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0) {

+    RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;

+    RCC->AHB1LPENR |= RCC_AHB1LPENR_DMA2LPEN;

+  }

+

+  /* Putting the stream in a safe state.*/

+  dmaStreamDisable(dmastp);

+  dmaStreamClearInterrupt(dmastp);

+  dmastp->channel->CR = STM32_DMA_CR_RESET_VALUE;

+  dmastp->channel->FCR = STM32_DMA_FCR_RESET_VALUE;

+

+  /* Enables the associated IRQ vector if a callback is defined.*/

+  if (func != NULL)

+    NVICEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));

+

+  return FALSE;

+}

+

+/**

+ * @brief   Releases a DMA stream.

+ * @details The stream is freed and, if required, the DMA clock disabled.

+ *          Trying to release a unallocated stream is an illegal operation

+ *          and is trapped if assertions are enabled.

+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().

+ * @post    The stream is again available.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

+ *

+ * @special

+ */

+void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {

+

+  chDbgCheck(dmastp != NULL, "dmaRelease");

+

+  /* Check if the streams is not taken.*/

+  chDbgAssert((dma_streams_mask & dmastp->mask) != 0,

+              "dmaRelease(), #1", "not allocated");

+

+  /* Disables the associated IRQ vector.*/

+  NVICDisableVector(dmastp->vector);

+

+  /* Marks the stream as not allocated.*/

+  dma_streams_mask &= ~(1 << dmastp->selfindex);

+

+  /* Shutting down clocks that are no more required, if any.*/

+  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0) {

+    RCC->AHB1ENR &= ~RCC_AHB1ENR_DMA1EN;

+    RCC->AHB1LPENR &= ~RCC_AHB1LPENR_DMA1LPEN;

+  }

+  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0) {

+    RCC->AHB1ENR &= ~RCC_AHB1ENR_DMA2EN;

+    RCC->AHB1LPENR &= ~RCC_AHB1LPENR_DMA2LPEN;

+  }

+}

+

+#endif /* STM32_DMA_REQUIRED */

+

+/** @} */

diff --git a/os/hal/platforms/STM32F2xx/stm32_dma.h b/os/hal/platforms/STM32F2xx/stm32_dma.h
new file mode 100644
index 000000000..af18497fc
--- /dev/null
+++ b/os/hal/platforms/STM32F2xx/stm32_dma.h
@@ -0,0 +1,327 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,

+                 2011 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    DMAv2/stm32_dma.h

+ * @brief   Enhanced-DMA helper driver header.

+ * @note    This file requires definitions from the ST STM32F2xx header file

+ *          stm32f2xx.h.

+ *

+ * @addtogroup STM32_DMA

+ * @{

+ */

+

+#ifndef _STM32_DMA_H_

+#define _STM32_DMA_H_

+

+/*===========================================================================*/

+/* Driver constants.                                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   Total number of DMA streams.

+ * @note    This is the total number of streams among all the DMA units.

+ */

+#define STM32_DMA_STREAMS           16

+

+/**

+ * @brief   Mask of the ISR bits passed to the DMA callback functions.

+ */

+#define STM32_DMA_ISR_MASK          0x3D

+

+/**

+ * @name    DMA streams identifiers

+ * @{

+ */

+#define STM32_DMA1_STREAM0          (&_stm32_dma_streams[0])

+#define STM32_DMA1_STREAM1          (&_stm32_dma_streams[1])

+#define STM32_DMA1_STREAM2          (&_stm32_dma_streams[2])

+#define STM32_DMA1_STREAM3          (&_stm32_dma_streams[3])

+#define STM32_DMA1_STREAM4          (&_stm32_dma_streams[4])

+#define STM32_DMA1_STREAM5          (&_stm32_dma_streams[5])

+#define STM32_DMA1_STREAM6          (&_stm32_dma_streams[6])

+#define STM32_DMA1_STREAM7          (&_stm32_dma_streams[7])

+#define STM32_DMA2_STREAM0          (&_stm32_dma_streams[8])

+#define STM32_DMA2_STREAM1          (&_stm32_dma_streams[9])

+#define STM32_DMA2_STREAM2          (&_stm32_dma_streams[10])

+#define STM32_DMA2_STREAM3          (&_stm32_dma_streams[11])

+#define STM32_DMA2_STREAM4          (&_stm32_dma_streams[12])

+#define STM32_DMA2_STREAM5          (&_stm32_dma_streams[13])

+#define STM32_DMA2_STREAM6          (&_stm32_dma_streams[14])

+#define STM32_DMA2_STREAM7          (&_stm32_dma_streams[15])

+/** @} */

+

+/**

+ * @name    CR register constants common to all DMA types

+ */

+#define STM32_DMA_CR_EN             DMA_SxCR_EN

+#define STM32_DMA_CR_TEIE           DMA_SxCR_TEIE

+#define STM32_DMA_CR_HTIE           DMA_SxCR_HTIE

+#define STM32_DMA_CR_TCIE           DMA_SxCR_TCIE

+#define STM32_DMA_CR_DIR_MASK       DMA_SxCR_DIR

+#define STM32_DMA_CR_DIR_P2M        0

+#define STM32_DMA_CR_DIR_M2P        DMA_SxCR_DIR_0

+#define STM32_DMA_CR_DIR_M2M        DMA_SxCR_DIR_1

+#define STM32_DMA_CR_CIRC           DMA_SxCR_CIRC

+#define STM32_DMA_CR_PINC           DMA_SxCR_PINC

+#define STM32_DMA_CR_MINC           DMA_SxCR_MINC

+#define STM32_DMA_CR_PSIZE_MASK     DMA_SxCR_PSIZE

+#define STM32_DMA_CR_PSIZE_BYTE     0

+#define STM32_DMA_CR_PSIZE_HWORD    DMA_SxCR_PSIZE_0

+#define STM32_DMA_CR_PSIZE_WORD     DMA_SxCR_PSIZE_1

+#define STM32_DMA_CR_MSIZE_MASK     DMA_SxCR_MSIZE

+#define STM32_DMA_CR_MSIZE_BYTE     0

+#define STM32_DMA_CR_MSIZE_HWORD    DMA_SxCR_MSIZE_0

+#define STM32_DMA_CR_MSIZE_WORD     DMA_SxCR_MSIZE_1

+#define STM32_DMA_CR_PL_MASK        DMA_SxCR_PL

+#define STM32_DMA_CR_PL(n)          ((n) << 16)

+/** @} */

+

+/**

+ * @name    CR register constants only found in STM32F2xx

+ */

+#define STM32_DMA_CR_DMEIE          DMA_SxCR_DMEIE

+#define STM32_DMA_CR_PFCTRL         DMA_SxCR_PFCTRL

+#define STM32_DMA_CR_PINCOS         DMA_SxCR_PINCOS

+#define STM32_DMA_CR_DBM            DMA_SxCR_DBM

+#define STM32_DMA_CR_CT             DMA_SxCR_CT

+#define STM32_DMA_CR_PBURST_MASK    DMA_SxCR_PBURST

+#define STM32_DMA_CR_PBURST_SINGLE  0

+#define STM32_DMA_CR_PBURST_INCR4   DMA_SxCR_PBURST_0

+#define STM32_DMA_CR_PBURST_INCR8   DMA_SxCR_PBURST_1

+#define STM32_DMA_CR_PBURST_INCR16  (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1)

+#define STM32_DMA_CR_MBURST_MASK    DMA_SxCR_MBURST

+#define STM32_DMA_CR_MBURST_SINGLE  0

+#define STM32_DMA_CR_MBURST_INCR4   DMA_SxCR_MBURST_0

+#define STM32_DMA_CR_MBURST_INCR8   DMA_SxCR_MBURST_1

+#define STM32_DMA_CR_MBURST_INCR16  (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1)

+#define STM32_DMA_CR_CHSEL_MASK     DMA_SxCR_CHSEL

+#define STM32_DMA_CR_CHSEL(n)       ((n) << 25)

+/** @} */

+

+/**

+ * @name    FCR register constants only found in STM32F2xx

+ */

+#define STM32_DMA_FCR_FEIE          DMA_SxFCR_FEIE

+#define STM32_DMA_FCR_FS_MASK       DMA_SxFCR_FS

+#define STM32_DMA_FCR_DMDIS         DMA_SxFCR_DMDIS

+#define STM32_DMA_FCR_FTH_MASK      DMA_SxFCR_FTH

+#define STM32_DMA_FCR_FTH_1Q        0

+#define STM32_DMA_FCR_FTH_HALF      DMA_SxFCR_FTH_0

+#define STM32_DMA_FCR_FTH_3Q        DMA_SxFCR_FTH_1

+#define STM32_DMA_FCR_FTH_FULL      (DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1)

+/** @} */

+

+/**

+ * @name    Status flags passed to the ISR callbacks

+ */

+#define STM32_DMA_ISR_FEIF          DMA_LISR_FEIF0

+#define STM32_DMA_ISR_DMEIF         DMA_LISR_DMEIF0

+#define STM32_DMA_ISR_TEIF          DMA_LISR_TEIF0

+#define STM32_DMA_ISR_HTIF          DMA_LISR_HTIF0

+#define STM32_DMA_ISR_TCIF          DMA_LISR_TCIF0

+/** @} */

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Derived constants and error checks.                                       */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   STM32 DMA stream descriptor structure.

+ */

+typedef struct {

+  DMA_Channel_TypeDef   *channel;       /**< @brief Associated DMA channel. */

+  volatile uint32_t     *ifcr;          /**< @brief Associated IFCR reg.    */

+  uint8_t               ishift;         /**< @brief Bits offset in xIFCR

+                                             register.                      */

+  uint8_t               selfindex;      /**< @brief Index to self in array. */

+  uint8_t               vector;         /**< @brief Associated IRQ vector.  */

+} stm32_dma_stream_t;

+

+/**

+ * @brief   STM32 DMA ISR function type.

+ *

+ * @param[in] p         parameter for the registered function

+ * @param[in] flags     pre-shifted content of the xISR register, the bits

+ *                      are aligned to bit zero

+ */

+typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);

+

+/*===========================================================================*/

+/* Driver macros.                                                            */

+/*===========================================================================*/

+

+/**

+ * @brief   Associates a peripheral data register to a DMA stream.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

+ * @param[in] addr      value to be written in the PAR register

+ *

+ * @special

+ */

+#define dmaStreamSetPeripheral(dmastp, addr) {                              \

+  (dmastp)->stream->PAR  = (uint32_t)(addr);                                \

+}

+

+/**

+ * @brief   Associates a memory destination to a DMA stream.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

+ * @param[in] addr      value to be written in the M0AR register

+ *

+ * @special

+ */

+#define dmaStreamSetMemory0(dmastp, addr) {                                 \

+  (dmastp)->stream->M0AR  = (uint32_t)(addr);                               \

+}

+

+/**

+ * @brief   Associates an alternate memory destination to a DMA stream.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

+ * @param[in] addr      value to be written in the M1AR register

+ *

+ * @special

+ */

+#define dmaStreamSetMemory1(dmastp, addr) {                                 \

+  (dmastp)->stream->M1AR  = (uint32_t)(addr);                               \

+}

+

+/**

+ * @brief   Sets the number of transfers to be performed.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

+ * @param[in] size      value to be written in the CNDTR register

+ *

+ * @special

+ */

+#define dmaStreamSetTransactionSize(dmastp, size) {                         \

+  (dmastp)->stream->NDTR  = (uint32_t)(size);                               \

+}

+

+/**

+ * @brief   Returns the number of transfers to be performed.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

+ * @return              The number of transfers to be performed.

+ *

+ * @special

+ */

+#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->stream->NDTR))

+

+/**

+ * @brief   Programs the stream mode settings.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

+ * @param[in] mode      value to be written in the CR register

+ *

+ * @special

+ */

+#define dmaStreamSetMode(dmastp, mode) {                                    \

+  (dmastp)->stream->CR  = (uint32_t)(mode);                                 \

+}

+

+/**

+ * @brief   Programs the stream FIFO settings.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

+ * @param[in] mode      value to be written in the FCR register

+ *

+ * @special

+ */

+#define dmaStreamSetFIFO(dmastp, mode) {                                    \

+  (dmastp)->stream->FCR = (uint32_t)(mode);                                 \

+}

+

+/**

+ * @brief   DMA stream enable.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dmachp    pointer to a stm32_dma_stream_t structure

+ *

+ * @special

+ */

+#define dmaStreamEnable(dmachp) {                                           \

+  (dmastp)->stream->CR |= STM32_DMA_CR_EN;                                  \

+}

+

+/**

+ * @brief   DMA stream disable.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

+ *

+ * @special

+ */

+#define dmaStreamDisable(dmastp) {                                          \

+  (dmastp)->stream->CR &= ~STM32_DMA_CR_EN;                                 \

+}

+

+/**

+ * @brief   DMA stream interrupt sources clear.

+ * @note    This function can be invoked in both ISR or thread context.

+ *

+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

+ *

+ * @special

+ */

+#define dmaStreamClearInterrupt(dmastp) {                                   \

+  *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift;                 \

+}

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+#if !defined(__DOXYGEN__)

+extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];

+#endif

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+  void dmaInit(void);

+  bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,

+                           uint32_t priority,

+                           stm32_dmaisr_t func,

+                           void *param);

+  void dmaStreamRelease(const stm32_dma_stream_t *dmastp);

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* _STM32_DMA_H_ */

+

+/** @} */