Provisional STM32F2xx support.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3649 35acf78f-673a-0410-8e92-d51de3d6d3f4

1 files changed, 26 insertions, 20 deletions

diff --git a/os/hal/platforms/STM32F2xx/hal_lld.c b/os/hal/platforms/STM32F2xx/hal_lld.c
index 2d5d56895..2b3894bdd 100644
--- a/os/hal/platforms/STM32F2xx/hal_lld.c
+++ b/os/hal/platforms/STM32F2xx/hal_lld.c
@@ -19,8 +19,8 @@
 */

 

 /**

- * @file    STM32F2xx/hal_lld.c

- * @brief   STM32F2xx HAL subsystem low level driver source.

+ * @file    STM32F4xx/hal_lld.c

+ * @brief   STM32F4xx HAL subsystem low level driver source.

  *

  * @addtogroup HAL

  * @{

@@ -56,11 +56,13 @@
  */

 void hal_lld_init(void) {

 

-  /* Reset of all peripherals.*/

-//  RCC->APB1RSTR = 0xFFFFFFFF;

-//  RCC->APB2RSTR = 0xFFFFFFFF;

-//  RCC->APB1RSTR = 0;

-//  RCC->APB2RSTR = 0;

+  /* Reset of all peripherals. AHB3 is not reseted because it could have

+     been initialized in the board initialization file (board.c).*/

+  rccResetAHB1(!0);

+  rccResetAHB2(!0);

+  rccResetAHB3(!0);

+  rccResetAPB1(!RCC_APB1RSTR_PWRRST);

+  rccResetAPB2(!0);

 

   /* SysTick initialization using the system clock.*/

   SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;

@@ -69,7 +71,10 @@ void hal_lld_init(void) {
                   SysTick_CTRL_ENABLE_Msk |

                   SysTick_CTRL_TICKINT_Msk;

 

-  

+#if STM32_PVD_ENABLE

+  /* Programmable voltage detector initialization */

+  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);

+#endif /* STM32_PVD_ENABLE */

 

 #if defined(STM32_DMA_REQUIRED)

   dmaInit();

@@ -83,16 +88,15 @@ void hal_lld_init(void) {
  *

  * @special

  */

-#if defined(STM32F2XX) || defined(__DOXYGEN__)

-/**

- * @brief   Clocks and internal voltage initialization.

- */

 void stm32_clock_init(void) {

 

 #if !STM32_NO_INIT

   /* PWR clock enable.*/

   RCC->APB1ENR = RCC_APB1ENR_PWREN;

 

+  /* PWR initialization.*/

+  PWR->CR = 0;

+

   /* Initial clocks setup and wait for HSI stabilization, the MSI clock is

      always enabled because it is the fallback clock when PLL the fails.*/

   RCC->CR |= RCC_CR_HSION;

@@ -134,7 +138,7 @@ void stm32_clock_init(void) {
 

 #if STM32_ACTIVATE_PLLI2S

   /* PLLI2S activation.*/

-  RCC->PLLI2SCFGR = STM32_PLI2SR_VALUE | STM32_PLLI2SN_VALUE;

+  RCC->PLLI2SCFGR = STM32_PLLI2SR_VALUE | STM32_PLLI2SN_VALUE;

   RCC->CR |= RCC_CR_PLLI2SON;

   while (!(RCC->CR & RCC_CR_PLLI2SRDY))

     ;                           /* Waits until PLLI2S is stable.            */

@@ -144,19 +148,21 @@ void stm32_clock_init(void) {
   RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |

                STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;

 

-  /* Flash setup.                                                           */

-  FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | STM32_FLASHBITS;

+  /* Flash setup.*/

+  FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN |

+               STM32_FLASHBITS;

 

-  /* Switching to the configured clock source if it is different from MSI.  */

+  /* Switching to the configured clock source if it is different from MSI.*/

 #if (STM32_SW != STM32_SW_HSI)

-  RCC->CFGR |= STM32_SW; /* Switches on the selected clock source.          */

+  RCC->CFGR |= STM32_SW;        /* Switches on the selected clock source.   */

   while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))

     ;

 #endif

 #endif /* STM32_NO_INIT */

+

+  /* SYSCFG clock enabled here because it is a multi-functional unit shared

+     among multiple drivers.*/

+  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);

 }

-#else

-void stm32_clock_init(void) {}

-#endif

 

 /** @} */