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| author | barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-01-04 20:03:49 +0000 |
|---|---|---|
| committer | barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-01-04 20:03:49 +0000 |
| commit | c506b8f2b1bf2446442040cd3f00f8750754d5aa (patch) | |
| tree | 97832a449711617e087d759b9d84bdf49b6a0d74 /os/hal/platforms/STM32F1xx | |
| parent | 205d56e9208c640543733f0b7f7088db21a371eb (diff) | |
| download | ChibiOS-c506b8f2b1bf2446442040cd3f00f8750754d5aa.tar.gz ChibiOS-c506b8f2b1bf2446442040cd3f00f8750754d5aa.tar.bz2 ChibiOS-c506b8f2b1bf2446442040cd3f00f8750754d5aa.zip | |
PVD. Checked compilability on F1x, L1x, F4x. Testhal fro F1x
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/pvd2_dev@3732 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F1xx')
| -rw-r--r-- | os/hal/platforms/STM32F1xx/hal_lld.c | 6 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F1xx/hal_lld.h | 27 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F1xx/stm32_rcc.h | 32 |
3 files changed, 65 insertions, 0 deletions
diff --git a/os/hal/platforms/STM32F1xx/hal_lld.c b/os/hal/platforms/STM32F1xx/hal_lld.c index 0f2d490d6..8afaf39a2 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld.c +++ b/os/hal/platforms/STM32F1xx/hal_lld.c @@ -73,6 +73,12 @@ void hal_lld_init(void) { #if defined(STM32_DMA_REQUIRED)
dmaInit();
#endif
+
+ /* Programmable voltage detector enable. */
+#if STM32_PVD_ENABLE
+ rccEnablePWRInterface(FALSE);
+ PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
+#endif /* STM32_PVD_ENABLE */
}
/**
diff --git a/os/hal/platforms/STM32F1xx/hal_lld.h b/os/hal/platforms/STM32F1xx/hal_lld.h index 4e1ca3f35..cf8e09cbe 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld.h +++ b/os/hal/platforms/STM32F1xx/hal_lld.h @@ -48,10 +48,37 @@ /*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
+/**
+ * @name PWR_CR register bits definitions
+ * @{
+ */
+#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
+#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 0. */
+/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
+/**
+ * @brief Enables or disables the programmable voltage detector.
+ */
+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
+#define STM32_PVD_ENABLE FALSE
+#endif
+
+/**
+ * @brief Sets voltage level for programmable voltage detector.
+ */
+#if !defined(STM32_PLS) || defined(__DOXYGEN__)
+#define STM32_PLS STM32_PLS_LEV0
+#endif
/*===========================================================================*/
/* Derived constants and error checks. */
diff --git a/os/hal/platforms/STM32F1xx/stm32_rcc.h b/os/hal/platforms/STM32F1xx/stm32_rcc.h index aa55d4fca..41cf725cb 100644 --- a/os/hal/platforms/STM32F1xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F1xx/stm32_rcc.h @@ -244,6 +244,38 @@ /** @} */
/**
+ * @brief PWR interface specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the PWR interface clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
+
+/**
+ * @brief Disables PWR interface clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_BKPEN, lp)
+
+/**
+ * @brief Resets the PWR interface.
+ *
+ * @api
+ */
+#define rccResetPWRInterface() rccResetAPB1(RCC_APB1ENR_BKPRST)
+/** @} */
+
+/**
* @brief CAN peripherals specific RCC operations
* @{
*/
|