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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-05-17 16:47:17 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-05-17 16:47:17 +0000 |
| commit | 76ac6302c73df7ab7da020b3ce412d2bdeafb2ea (patch) | |
| tree | 5ea53935cdb6f7dc794ce82404ade7264e4924ed /os/hal/platforms/STM32F1xx | |
| parent | d25f85f0ea9b8340a9f16000c43f218a34e56477 (diff) | |
| download | ChibiOS-76ac6302c73df7ab7da020b3ce412d2bdeafb2ea.tar.gz ChibiOS-76ac6302c73df7ab7da020b3ce412d2bdeafb2ea.tar.bz2 ChibiOS-76ac6302c73df7ab7da020b3ce412d2bdeafb2ea.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4204 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F1xx')
| -rw-r--r-- | os/hal/platforms/STM32F1xx/hal_lld_f100.h | 2 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F1xx/hal_lld_f103.h | 10 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h | 2 |
3 files changed, 10 insertions, 4 deletions
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h index 5875279c2..4a01eb739 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -626,7 +626,7 @@ #endif
/**
- * @brief Clock source selecting. LSI by default.
+ * @brief RTC clock source.
*/
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
#define STM32_RTCSEL STM32_RTCSEL_LSI
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h index 8e35114ff..02b08cb8f 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h @@ -178,7 +178,12 @@ #define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */
#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */
#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
+/** @} */
+/**
+ * @name RCC_BDCR register bits definitions
+ * @{
+ */
#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
@@ -953,7 +958,7 @@ #endif
/**
- * @brief Clock source selecting. LSI by default.
+ * @brief RTC clock source.
*/
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
#define STM32_RTCSEL STM32_RTCSEL_LSI
@@ -1008,7 +1013,8 @@ #endif
#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
- ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && (STM32_PLLSRC == STM32_PLLSRC_HSE))
+ ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE))
#error "HSE not enabled, required by STM32_MCOSEL"
#endif
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h index bce886c44..139402bd4 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -573,7 +573,7 @@ #endif
/**
- * @brief Clock source selecting. LSI by default.
+ * @brief RTC clock source.
*/
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
#define STM32_RTCSEL STM32_RTCSEL_HSEDIV
|