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| author | barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-09-20 07:18:29 +0000 |
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| committer | barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-09-20 07:18:29 +0000 |
| commit | 3035afea9de7fbf89c5c3852abeaf47780df4613 (patch) | |
| tree | 8ee14c5480477066446a1bac0f08fa408332c741 /os/hal/platforms/STM32F1xx | |
| parent | da3d1eae7b4035fb916e14ba853a5cf2aa0f70cd (diff) | |
| download | ChibiOS-3035afea9de7fbf89c5c3852abeaf47780df4613.tar.gz ChibiOS-3035afea9de7fbf89c5c3852abeaf47780df4613.tar.bz2 ChibiOS-3035afea9de7fbf89c5c3852abeaf47780df4613.zip | |
RTC.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3357 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F1xx')
| -rw-r--r-- | os/hal/platforms/STM32F1xx/hal_lld_f100.h | 5 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h | 5 |
2 files changed, 10 insertions, 0 deletions
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h index 60e42ece4..5cabd9788 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -87,6 +87,11 @@ #define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */
#define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
+#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock */
+#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock */
+#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock */
+#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as RTC clock */
+
/*===========================================================================*/
/* Platform specific friendly IRQ names. */
/*===========================================================================*/
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h index 52c124d2d..caed49aca 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -92,6 +92,11 @@ #define STM32_MCO_XT1 (10 << 24) /**< XT1 clock on MCO pin. */
#define STM32_MCO_PLL3 (11 << 24) /**< PLL3 clock on MCO pin. */
+#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock */
+#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock */
+#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock */
+#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as RTC clock */
+
/* RCC_CFGR2 register bits definitions.*/
#define STM32_PREDIV1SRC_HSE (0 << 16) /**< PREDIV1 source is HSE. */
#define STM32_PREDIV1SRC_PLL2 (1 << 16) /**< PREDIV1 source is PLL2. */
|