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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-01-08 11:38:57 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-01-08 11:38:57 +0000 |
| commit | 040c4026cc184427e6f37495fa7fe6ce80d67d35 (patch) | |
| tree | 2645dbf643babb822dde86bcf4481612de378524 /os/hal/platforms/STM32F1xx/hal_lld.h | |
| parent | 32d143ae634416a6cd40db219352b707cea2dcd3 (diff) | |
| download | ChibiOS-040c4026cc184427e6f37495fa7fe6ce80d67d35.tar.gz ChibiOS-040c4026cc184427e6f37495fa7fe6ce80d67d35.tar.bz2 ChibiOS-040c4026cc184427e6f37495fa7fe6ce80d67d35.zip | |
STM32F1xx devices clock configuration updated to make it similar to the newer STM32 devices.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3763 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F1xx/hal_lld.h')
| -rw-r--r-- | os/hal/platforms/STM32F1xx/hal_lld.h | 52 |
1 files changed, 50 insertions, 2 deletions
diff --git a/os/hal/platforms/STM32F1xx/hal_lld.h b/os/hal/platforms/STM32F1xx/hal_lld.h index 0d8e0b8b3..ad6f117c8 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld.h +++ b/os/hal/platforms/STM32F1xx/hal_lld.h @@ -50,6 +50,14 @@ /*===========================================================================*/
/**
+ * @name Internal clock sources
+ * @{
+ */
+#define STM32_HSICLK 8000000 /**< High speed internal clock. */
+#define STM32_LSICLK 40000 /**< Low speed internal clock. */
+/** @} */
+
+/**
* @name PWR_CR register bits definitions
* @{
*/
@@ -69,6 +77,17 @@ /*===========================================================================*/
/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Disables the PWR/RCC initialization in the HAL.
+ */
+#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
+#define STM32_NO_INIT FALSE
+#endif
+
+/**
* @brief Enables or disables the programmable voltage detector.
*/
#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
@@ -82,6 +101,35 @@ #define STM32_PLS STM32_PLS_LEV0
#endif
+/**
+ * @brief Enables or disables the HSI clock source.
+ */
+#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI_ENABLED TRUE
+#endif
+
+/**
+ * @brief Enables or disables the LSI clock source.
+ */
+#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSI_ENABLED FALSE
+#endif
+
+/**
+ * @brief Enables or disables the HSE clock source.
+ */
+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSE_ENABLED TRUE
+#endif
+
+/**
+ * @brief Enables or disables the LSE clock source.
+ */
+#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSE_ENABLED FALSE
+#endif
+/** @} */
+
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
@@ -160,13 +208,13 @@ typedef uint32_t halrtcnt_t; /**
* @brief Realtime counter frequency.
* @note The DWT_CYCCNT register is incremented directly by the system
- * clock so this function returns STM32_SYSCLK.
+ * clock so this function returns STM32_HCLK.
*
* @return The realtime counter frequency of type halclock_t.
*
* @notapi
*/
-#define hal_lld_get_counter_frequency() STM32_SYSCLK
+#define hal_lld_get_counter_frequency() STM32_HCLK
/*===========================================================================*/
/* External declarations. */
|