diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-06-21 16:25:11 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-06-21 16:25:11 +0000 |
| commit | 43011f1886d70446f3f48f79cb99be2a07b6d33f (patch) | |
| tree | f2ec297bc12a94047c6a01978931f28141663aaa /os/hal/platforms/STM32F0xx | |
| parent | 8fb998f0a5bcc315fc45a3af1707551de03af63b (diff) | |
| download | ChibiOS-43011f1886d70446f3f48f79cb99be2a07b6d33f.tar.gz ChibiOS-43011f1886d70446f3f48f79cb99be2a07b6d33f.tar.bz2 ChibiOS-43011f1886d70446f3f48f79cb99be2a07b6d33f.zip | |
STM32 support enhancements, some other fixes.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4313 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F0xx')
| -rw-r--r-- | os/hal/platforms/STM32F0xx/ext_lld_isr.c | 207 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F0xx/ext_lld_isr.h | 111 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F0xx/hal_lld.h | 3 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F0xx/platform.mk | 17 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F0xx/stm32_isr.h | 73 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F0xx/stm32f0xx.h | 454 |
6 files changed, 629 insertions, 236 deletions
diff --git a/os/hal/platforms/STM32F0xx/ext_lld_isr.c b/os/hal/platforms/STM32F0xx/ext_lld_isr.c new file mode 100644 index 000000000..acfc42024 --- /dev/null +++ b/os/hal/platforms/STM32F0xx/ext_lld_isr.c @@ -0,0 +1,207 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file STM32F0xx/ext_lld_isr.c
+ * @brief STM32F0xx EXT subsystem low level driver ISR code.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+#include "ext_lld_isr.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief EXTI[0] interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(EXTI0_1_IRQHandler) {
+ uint32_t pr;
+
+ CH_IRQ_PROLOGUE();
+
+ pr = EXTI->PR & ((1 << 0) | (1 << 1));
+ EXTI->PR = pr;
+ if (pr & (1 << 0))
+ EXTD1.config->channels[0].cb(&EXTD1, 0);
+ if (pr & (1 << 1))
+ EXTD1.config->channels[1].cb(&EXTD1, 1);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[1] interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(EXTI2_3_IRQHandler) {
+ uint32_t pr;
+
+ CH_IRQ_PROLOGUE();
+
+ pr = EXTI->PR & ((2 << 0) | (3 << 1));
+ EXTI->PR = pr;
+ if (pr & (1 << 2))
+ EXTD1.config->channels[2].cb(&EXTD1, 2);
+ if (pr & (1 << 3))
+ EXTD1.config->channels[3].cb(&EXTD1, 3);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[4]...EXTI[15] interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
+ uint32_t pr;
+
+ CH_IRQ_PROLOGUE();
+
+ pr = EXTI->PR & ((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) |
+ (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) |
+ (1 << 14) | (1 << 15));
+ EXTI->PR = pr;
+ if (pr & (1 << 4))
+ EXTD1.config->channels[4].cb(&EXTD1, 4);
+ if (pr & (1 << 5))
+ EXTD1.config->channels[5].cb(&EXTD1, 5);
+ if (pr & (1 << 6))
+ EXTD1.config->channels[6].cb(&EXTD1, 6);
+ if (pr & (1 << 7))
+ EXTD1.config->channels[7].cb(&EXTD1, 7);
+ if (pr & (1 << 8))
+ EXTD1.config->channels[8].cb(&EXTD1, 8);
+ if (pr & (1 << 9))
+ EXTD1.config->channels[9].cb(&EXTD1, 9);
+ if (pr & (1 << 10))
+ EXTD1.config->channels[10].cb(&EXTD1, 10);
+ if (pr & (1 << 11))
+ EXTD1.config->channels[11].cb(&EXTD1, 11);
+ if (pr & (1 << 12))
+ EXTD1.config->channels[12].cb(&EXTD1, 12);
+ if (pr & (1 << 13))
+ EXTD1.config->channels[13].cb(&EXTD1, 13);
+ if (pr & (1 << 14))
+ EXTD1.config->channels[14].cb(&EXTD1, 14);
+ if (pr & (1 << 15))
+ EXTD1.config->channels[15].cb(&EXTD1, 15);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[16] interrupt handler (PVD).
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(PVD_IRQHandler) {
+
+ CH_IRQ_PROLOGUE();
+
+ EXTI->PR = (1 << 16);
+ EXTD1.config->channels[16].cb(&EXTD1, 16);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[17] interrupt handler (RTC).
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(RTC_IRQHandler) {
+
+ CH_IRQ_PROLOGUE();
+
+ EXTI->PR = (1 << 17);
+ EXTD1.config->channels[17].cb(&EXTD1, 17);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_enable(void) {
+
+ nvicEnableVector(EXTI0_1_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_1_IRQ_PRIORITY));
+ nvicEnableVector(EXTI2_3_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_3_IRQ_PRIORITY));
+ nvicEnableVector(EXTI4_15_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_15_IRQ_PRIORITY));
+ nvicEnableVector(PVD_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
+ nvicEnableVector(RTC_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
+}
+
+/**
+ * @brief Disables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_disable(void) {
+
+ nvicDisableVector(EXTI0_1_IRQn);
+ nvicDisableVector(EXTI2_3_IRQn);
+ nvicDisableVector(EXTI4_15_IRQn);
+ nvicDisableVector(PVD_IRQn);
+ nvicDisableVector(RTC_IRQn);
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F0xx/ext_lld_isr.h b/os/hal/platforms/STM32F0xx/ext_lld_isr.h new file mode 100644 index 000000000..6b2e49655 --- /dev/null +++ b/os/hal/platforms/STM32F0xx/ext_lld_isr.h @@ -0,0 +1,111 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file STM32F0xx/ext_lld_isr.h
+ * @brief STM32F0xx EXT subsystem low level driver ISR header.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#ifndef _EXT_LLD_ISR_H_
+#define _EXT_LLD_ISR_H_
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief EXTI0..1 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI0_1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI2..3 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI2_3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI4..15 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI4_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI16 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI17 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI17_IRQ_PRIORITY 3
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void ext_lld_exti_irq_enable(void);
+ void ext_lld_exti_irq_disable(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_EXT */
+
+#endif /* _EXT_LLD_ISR_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h index 93403c91f..158407527 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.h +++ b/os/hal/platforms/STM32F0xx/hal_lld.h @@ -950,7 +950,8 @@ /* External declarations. */
/*===========================================================================*/
-/* STM32 DMA and RCC helpers.*/
+/* STM32 ISR, DMA and RCC helpers.*/
+#include "stm32_isr.h"
#include "stm32_dma.h"
#include "stm32_rcc.h"
diff --git a/os/hal/platforms/STM32F0xx/platform.mk b/os/hal/platforms/STM32F0xx/platform.mk index 9c0e709df..43a6d3328 100644 --- a/os/hal/platforms/STM32F0xx/platform.mk +++ b/os/hal/platforms/STM32F0xx/platform.mk @@ -1,12 +1,15 @@ -# List of all the STM32F1xx platform files.
+# List of all the STM32F0xx platform files.
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
- ${CHIBIOS}/os/hal/platforms/STM32F0xx/adc_lld.c \
${CHIBIOS}/os/hal/platforms/STM32F0xx/hal_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c
+ ${CHIBIOS}/os/hal/platforms/STM32F0xx/adc_lld.c \
+ ${CHIBIOS}/os/hal/platforms/STM32F0xx/ext_lld_isr.c \
+ ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
+ ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
+ ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
+ ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
+ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx \
- ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
- ${CHIBIOS}/os/hal/platforms/STM32
+ ${CHIBIOS}/os/hal/platforms/STM32 \
+ ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2
diff --git a/os/hal/platforms/STM32F0xx/stm32_isr.h b/os/hal/platforms/STM32F0xx/stm32_isr.h new file mode 100644 index 000000000..408636b72 --- /dev/null +++ b/os/hal/platforms/STM32F0xx/stm32_isr.h @@ -0,0 +1,73 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file STM3F0xx/stm32_isr.h
+ * @brief ISR remapper driver header.
+ *
+ * @addtogroup STM32F0xx_ISR
+ * @{
+ */
+
+#ifndef _STM32_ISR_H_
+#define _STM32_ISR_H_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name ISR names and numbers remapping
+ * @{
+ */
+#define STM32_TIM1_UP_HANDLER TIM1_BRK_UP_TRG_COM_IRQHandler
+#define STM32_TIM1_CC_HANDLER TIM1_CC_IRQHandler
+#define STM32_TIM2_HANDLER TIM2_IRQHandler
+#define STM32_TIM3_HANDLER TIM3_IRQHandler
+
+#define STM32_TIM1_UP_NUMBER TIM1_BRK_UP_TRG_COM_IRQn
+#define STM32_TIM1_CC_NUMBER TIM1_CC_IRQn
+#define STM32_TIM2_NUMBER TIM2_IRQn
+#define STM32_TIM3_NUMBER TIM3_IRQn
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#endif /* _STM32_ISR_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F0xx/stm32f0xx.h b/os/hal/platforms/STM32F0xx/stm32f0xx.h index 74bc8ff10..b041e5e12 100644 --- a/os/hal/platforms/STM32F0xx/stm32f0xx.h +++ b/os/hal/platforms/STM32F0xx/stm32f0xx.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 23-March-2012
+ * @version V1.0.1
+ * @date 20-April-2012
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F0xx devices.
@@ -61,7 +61,7 @@ * @{
*/
-/* Uncomment the line below according to the target STM32F-0 device used in your
+/* Uncomment the line below according to the target STM32F0 device used in your
application
*/
@@ -71,8 +71,9 @@ /* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
- - STM32F0xx devices are STM32F050xx microcontrollers where the Flash memory
- density ranges between 32 and 64 Kbytes.
+ STM32F0xx devices are:
+ - STM32F050xx microcontrollers where the Flash memory density can go up to 32 Kbytes.
+ - STM32F051xx microcontrollers where the Flash memory density can go up to 64 Kbytes.
*/
#if !defined (STM32F0XX)
@@ -138,11 +139,11 @@ #endif /* LSE_VALUE */
/**
- * @brief STM32F0xx Standard Peripheral Library version number V1.0.0
+ * @brief STM32F0xx Standard Peripheral Library version number V1.0.1
*/
#define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
-#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\
|(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
@@ -2179,266 +2180,263 @@ typedef struct /* */
/******************************************************************************/
/******************** Bits definition for RTC_TR register *******************/
-#define RTC_TR_PM ((uint32_t)0x00400000) /*!< */
-#define RTC_TR_HT ((uint32_t)0x00300000) /*!< */
-#define RTC_TR_HT_0 ((uint32_t)0x00100000) /*!< */
-#define RTC_TR_HT_1 ((uint32_t)0x00200000) /*!< */
-#define RTC_TR_HU ((uint32_t)0x000F0000) /*!< */
-#define RTC_TR_HU_0 ((uint32_t)0x00010000) /*!< */
-#define RTC_TR_HU_1 ((uint32_t)0x00020000) /*!< */
-#define RTC_TR_HU_2 ((uint32_t)0x00040000) /*!< */
-#define RTC_TR_HU_3 ((uint32_t)0x00080000) /*!< */
-#define RTC_TR_MNT ((uint32_t)0x00007000) /*!< */
-#define RTC_TR_MNT_0 ((uint32_t)0x00001000) /*!< */
-#define RTC_TR_MNT_1 ((uint32_t)0x00002000) /*!< */
-#define RTC_TR_MNT_2 ((uint32_t)0x00004000) /*!< */
-#define RTC_TR_MNU ((uint32_t)0x00000F00) /*!< */
-#define RTC_TR_MNU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_TR_MNU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_TR_MNU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_TR_MNU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_TR_ST ((uint32_t)0x00000070) /*!< */
-#define RTC_TR_ST_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_TR_ST_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_TR_ST_2 ((uint32_t)0x00000040) /*!< */
-#define RTC_TR_SU ((uint32_t)0x0000000F) /*!< */
-#define RTC_TR_SU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_TR_SU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_TR_SU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_TR_SU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_DR register *******************/
-#define RTC_DR_YT ((uint32_t)0x00F00000) /*!< */
-#define RTC_DR_YT_0 ((uint32_t)0x00100000) /*!< */
-#define RTC_DR_YT_1 ((uint32_t)0x00200000) /*!< */
-#define RTC_DR_YT_2 ((uint32_t)0x00400000) /*!< */
-#define RTC_DR_YT_3 ((uint32_t)0x00800000) /*!< */
-#define RTC_DR_YU ((uint32_t)0x000F0000) /*!< */
-#define RTC_DR_YU_0 ((uint32_t)0x00010000) /*!< */
-#define RTC_DR_YU_1 ((uint32_t)0x00020000) /*!< */
-#define RTC_DR_YU_2 ((uint32_t)0x00040000) /*!< */
-#define RTC_DR_YU_3 ((uint32_t)0x00080000) /*!< */
-#define RTC_DR_WDU ((uint32_t)0x0000E000) /*!< */
-#define RTC_DR_WDU_0 ((uint32_t)0x00002000) /*!< */
-#define RTC_DR_WDU_1 ((uint32_t)0x00004000) /*!< */
-#define RTC_DR_WDU_2 ((uint32_t)0x00008000) /*!< */
-#define RTC_DR_MT ((uint32_t)0x00001000) /*!< */
-#define RTC_DR_MU ((uint32_t)0x00000F00) /*!< */
-#define RTC_DR_MU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_DR_MU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_DR_MU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_DR_MU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_DR_DT ((uint32_t)0x00000030) /*!< */
-#define RTC_DR_DT_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_DR_DT_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_DR_DU ((uint32_t)0x0000000F) /*!< */
-#define RTC_DR_DU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_DR_DU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_DR_DU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_DR_DU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_CR register *******************/
-#define RTC_CR_COE ((uint32_t)0x00800000) /*!< */
-#define RTC_CR_OSEL ((uint32_t)0x00600000) /*!< */
-#define RTC_CR_OSEL_0 ((uint32_t)0x00200000) /*!< */
-#define RTC_CR_OSEL_1 ((uint32_t)0x00400000) /*!< */
-#define RTC_CR_POL ((uint32_t)0x00100000) /*!< */
-#define RTC_CR_CALSEL ((uint32_t)0x00080000) /*!< */
-#define RTC_CR_BCK ((uint32_t)0x00040000) /*!< */
-#define RTC_CR_SUB1H ((uint32_t)0x00020000) /*!< */
-#define RTC_CR_ADD1H ((uint32_t)0x00010000) /*!< */
-#define RTC_CR_TSIE ((uint32_t)0x00008000) /*!< */
-#define RTC_CR_ALRAIE ((uint32_t)0x00001000) /*!< */
-#define RTC_CR_TSE ((uint32_t)0x00000800) /*!< */
-#define RTC_CR_ALRAE ((uint32_t)0x00000100) /*!< */
-#define RTC_CR_DCE ((uint32_t)0x00000080) /*!< */
-#define RTC_CR_FMT ((uint32_t)0x00000040) /*!< */
-#define RTC_CR_BYPSHAD ((uint32_t)0x00000020) /*!< */
-#define RTC_CR_REFCKON ((uint32_t)0x00000010) /*!< */
-#define RTC_CR_TSEDGE ((uint32_t)0x00000008) /*!< */
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_CALSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_DCE ((uint32_t)0x00000080)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
/******************** Bits definition for RTC_ISR register ******************/
-#define RTC_ISR_RECALPF ((uint32_t)0x00010000) /*!< */
-#define RTC_ISR_TAMP3F ((uint32_t)0x00008000) /*!< */
-#define RTC_ISR_TAMP2F ((uint32_t)0x00004000) /*!< */
-#define RTC_ISR_TAMP1F ((uint32_t)0x00002000) /*!< */
-#define RTC_ISR_TSOVF ((uint32_t)0x00001000) /*!< */
-#define RTC_ISR_TSF ((uint32_t)0x00000800) /*!< */
-#define RTC_ISR_ALRAF ((uint32_t)0x00000100) /*!< */
-#define RTC_ISR_INIT ((uint32_t)0x00000080) /*!< */
-#define RTC_ISR_INITF ((uint32_t)0x00000040) /*!< */
-#define RTC_ISR_RSF ((uint32_t)0x00000020) /*!< */
-#define RTC_ISR_INITS ((uint32_t)0x00000010) /*!< */
-#define RTC_ISR_SHPF ((uint32_t)0x00000008) /*!< */
-#define RTC_ISR_ALRAWF ((uint32_t)0x00000001) /*!< */
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
/******************** Bits definition for RTC_PRER register *****************/
-#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) /*!< */
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) /*!< */
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_ALRMAR register ***************/
-#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) /*!< */
-#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) /*!< */
-#define RTC_ALRMAR_DT ((uint32_t)0x30000000) /*!< */
-#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) /*!< */
-#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) /*!< */
-#define RTC_ALRMAR_DU ((uint32_t)0x0F000000) /*!< */
-#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) /*!< */
-#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) /*!< */
-#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) /*!< */
-#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) /*!< */
-#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) /*!< */
-#define RTC_ALRMAR_PM ((uint32_t)0x00400000) /*!< */
-#define RTC_ALRMAR_HT ((uint32_t)0x00300000) /*!< */
-#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) /*!< */
-#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) /*!< */
-#define RTC_ALRMAR_HU ((uint32_t)0x000F0000) /*!< */
-#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) /*!< */
-#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) /*!< */
-#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) /*!< */
-#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) /*!< */
-#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) /*!< */
-#define RTC_ALRMAR_MNT ((uint32_t)0x00007000) /*!< */
-#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) /*!< */
-#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) /*!< */
-#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) /*!< */
-#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) /*!< */
-#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) /*!< */
-#define RTC_ALRMAR_ST ((uint32_t)0x00000070) /*!< */
-#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) /*!< */
-#define RTC_ALRMAR_SU ((uint32_t)0x0000000F) /*!< */
-#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_WPR register ******************/
-#define RTC_WPR_KEY ((uint32_t)0x000000FF) /*!< */
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
/******************** Bits definition for RTC_SSR register ******************/
-#define RTC_SSR_SS ((uint32_t)0x0003FFFF) /*!< */
+#define RTC_SSR_SS ((uint32_t)0x0003FFFF)
/******************** Bits definition for RTC_SHIFTR register ***************/
-#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) /*!< */
-#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) /*!< */
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
/******************** Bits definition for RTC_TSTR register *****************/
-#define RTC_TSTR_PM ((uint32_t)0x00400000) /*!< */
-#define RTC_TSTR_HT ((uint32_t)0x00300000) /*!< */
-#define RTC_TSTR_HT_0 ((uint32_t)0x00100000) /*!< */
-#define RTC_TSTR_HT_1 ((uint32_t)0x00200000) /*!< */
-#define RTC_TSTR_HU ((uint32_t)0x000F0000) /*!< */
-#define RTC_TSTR_HU_0 ((uint32_t)0x00010000) /*!< */
-#define RTC_TSTR_HU_1 ((uint32_t)0x00020000) /*!< */
-#define RTC_TSTR_HU_2 ((uint32_t)0x00040000) /*!< */
-#define RTC_TSTR_HU_3 ((uint32_t)0x00080000) /*!< */
-#define RTC_TSTR_MNT ((uint32_t)0x00007000) /*!< */
-#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) /*!< */
-#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) /*!< */
-#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) /*!< */
-#define RTC_TSTR_MNU ((uint32_t)0x00000F00) /*!< */
-#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_TSTR_ST ((uint32_t)0x00000070) /*!< */
-#define RTC_TSTR_ST_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_TSTR_ST_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_TSTR_ST_2 ((uint32_t)0x00000040) /*!< */
-#define RTC_TSTR_SU ((uint32_t)0x0000000F) /*!< */
-#define RTC_TSTR_SU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_TSTR_SU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_TSTR_SU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_TSTR_SU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_TSDR register *****************/
-#define RTC_TSDR_WDU ((uint32_t)0x0000E000) /*!< */
-#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) /*!< */
-#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) /*!< */
-#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) /*!< */
-#define RTC_TSDR_MT ((uint32_t)0x00001000) /*!< */
-#define RTC_TSDR_MU ((uint32_t)0x00000F00) /*!< */
-#define RTC_TSDR_MU_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_TSDR_MU_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_TSDR_MU_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_TSDR_MU_3 ((uint32_t)0x00000800) /*!< */
-#define RTC_TSDR_DT ((uint32_t)0x00000030) /*!< */
-#define RTC_TSDR_DT_0 ((uint32_t)0x00000010) /*!< */
-#define RTC_TSDR_DT_1 ((uint32_t)0x00000020) /*!< */
-#define RTC_TSDR_DU ((uint32_t)0x0000000F) /*!< */
-#define RTC_TSDR_DU_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_TSDR_DU_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_TSDR_DU_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_TSDR_DU_3 ((uint32_t)0x00000008) /*!< */
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_TSSSR register ****************/
#define RTC_TSSSR_SS ((uint32_t)0x0003FFFF)
/******************** Bits definition for RTC_CAL register *****************/
-#define RTC_CAL_CALP ((uint32_t)0x00008000) /*!< */
-#define RTC_CAL_CALW8 ((uint32_t)0x00004000) /*!< */
-#define RTC_CAL_CALW16 ((uint32_t)0x00002000) /*!< */
-#define RTC_CAL_CALM ((uint32_t)0x000001FF) /*!< */
-#define RTC_CAL_CALM_0 ((uint32_t)0x00000001) /*!< */
-#define RTC_CAL_CALM_1 ((uint32_t)0x00000002) /*!< */
-#define RTC_CAL_CALM_2 ((uint32_t)0x00000004) /*!< */
-#define RTC_CAL_CALM_3 ((uint32_t)0x00000008) /*!< */
-#define RTC_CAL_CALM_4 ((uint32_t)0x00000010) /*!< */
-#define RTC_CAL_CALM_5 ((uint32_t)0x00000020) /*!< */
-#define RTC_CAL_CALM_6 ((uint32_t)0x00000040) /*!< */
-#define RTC_CAL_CALM_7 ((uint32_t)0x00000080) /*!< */
-#define RTC_CAL_CALM_8 ((uint32_t)0x00000100) /*!< */
+#define RTC_CAL_CALP ((uint32_t)0x00008000)
+#define RTC_CAL_CALW8 ((uint32_t)0x00004000)
+#define RTC_CAL_CALW16 ((uint32_t)0x00002000)
+#define RTC_CAL_CALM ((uint32_t)0x000001FF)
+#define RTC_CAL_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CAL_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CAL_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CAL_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CAL_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CAL_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CAL_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CAL_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CAL_CALM_8 ((uint32_t)0x00000100)
/******************** Bits definition for RTC_TAFCR register ****************/
-#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) /*!< */
-#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) /*!< */
-#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) /*!< */
-#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) /*!< */
-#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) /*!< */
-#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) /*!< */
-#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) /*!< */
-#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) /*!< */
-#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) /*!< */
-#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) /*!< */
-#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) /*!< */
-#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) /*!< */
-#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) /*!< */
-#define RTC_TAFCR_TAMP3EDGE ((uint32_t)0x00000040) /*!< */
-#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020) /*!< */
-#define RTC_TAFCR_TAMP2EDGE ((uint32_t)0x00000010) /*!< */
-#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008) /*!< */
-#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) /*!< */
-#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) /*!< */
-#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) /*!< */
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP2EDGE ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
/******************** Bits definition for RTC_ALRMASSR register *************/
-#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) /*!< */
-#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) /*!< */
-#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) /*!< */
-#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) /*!< */
-#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) /*!< */
-#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) /*!< */
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_BKP0R register ****************/
-#define RTC_BKP0R ((uint32_t)0xFFFFFFFF) /*!< */
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP1R register ****************/
-#define RTC_BKP1R ((uint32_t)0xFFFFFFFF) /*!< */
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP2R register ****************/
-#define RTC_BKP2R ((uint32_t)0xFFFFFFFF) /*!< */
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP3R register ****************/
-#define RTC_BKP3R ((uint32_t)0xFFFFFFFF) /*!< */
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP4R register ****************/
-#define RTC_BKP4R ((uint32_t)0xFFFFFFFF) /*!< */
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
/******************************************************************************/
/* */
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