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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-10-24 09:46:46 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-10-24 09:46:46 +0000 |
| commit | ca0b2a235d6b537896efeb11f263d7e103a92d82 (patch) | |
| tree | 3148ea55ee51596b608f905096c2d9384c07ea4b /os/hal/platforms/STM32F0xx/hal_lld.c | |
| parent | 7112dfa32e35f35998bf4ab05888317ef5aed59a (diff) | |
| download | ChibiOS-ca0b2a235d6b537896efeb11f263d7e103a92d82.tar.gz ChibiOS-ca0b2a235d6b537896efeb11f263d7e103a92d82.tar.bz2 ChibiOS-ca0b2a235d6b537896efeb11f263d7e103a92d82.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4778 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F0xx/hal_lld.c')
| -rw-r--r-- | os/hal/platforms/STM32F0xx/hal_lld.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c index 1e7a83e36..10b6db940 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.c +++ b/os/hal/platforms/STM32F0xx/hal_lld.c @@ -171,19 +171,20 @@ void stm32_clock_init(void) { ; /* Waits until LSI is stable. */
#endif
+ /* Clock settings.*/
+ RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE |
+ STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE |
+ STM32_HPRE;
+ RCC->CFGR3 = STM32_ADCSW | STM32_CECSW | STM32_I2C1SW |
+ STM32_USART1SW;
+
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
- RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY))
; /* Waits until PLL is stable. */
#endif
- /* Clock settings.*/
- RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE |
- STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE | STM32_HPRE;
- RCC->CFGR3 = STM32_ADCSW | STM32_CECSW | STM32_I2C1SW | STM32_USART1SW;
-
/* Flash setup and final clock selection. */
FLASH->ACR = STM32_FLASHBITS;
|