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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-12-06 10:53:16 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-12-06 10:53:16 +0000 |
| commit | 633098ebcd87d2a654deede6feff0d93fdabaebc (patch) | |
| tree | b1f97259ff9915cae042e4c419aca1897d0892c6 /os/hal/platforms/STM32F0xx/hal_lld.c | |
| parent | cc3cf07897dbd9f4fc27c6117c88fb7cbf85b1a6 (diff) | |
| download | ChibiOS-633098ebcd87d2a654deede6feff0d93fdabaebc.tar.gz ChibiOS-633098ebcd87d2a654deede6feff0d93fdabaebc.tar.bz2 ChibiOS-633098ebcd87d2a654deede6feff0d93fdabaebc.zip | |
STM32F3 SPI working, STM32F0 support update.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4879 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F0xx/hal_lld.c')
| -rw-r--r-- | os/hal/platforms/STM32F0xx/hal_lld.c | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c index 10b6db940..57b548ce3 100644 --- a/os/hal/platforms/STM32F0xx/hal_lld.c +++ b/os/hal/platforms/STM32F0xx/hal_lld.c @@ -29,10 +29,6 @@ #include "ch.h"
#include "hal.h"
-/* TODO: LSEBYP like in F3.*/
-/* TODO: LSEDRV like in F3.*/
-/* TODO: PREDIV like in F3.*/
-
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@@ -64,7 +60,13 @@ static void hal_lld_backup_domain_init(void) { /* If enabled then the LSE is started.*/
#if STM32_LSE_ENABLED
- RCC->BDCR |= RCC_BDCR_LSEON;
+#if defined(STM32_LSE_BYPASS)
+ /* LSE Bypass.*/
+ RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
+#else
+ /* No LSE Bypass.*/
+ RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON;
+#endif
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
#endif
@@ -172,10 +174,10 @@ void stm32_clock_init(void) { #endif
/* Clock settings.*/
- RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE |
- STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE |
- STM32_HPRE;
- RCC->CFGR3 = STM32_ADCSW | STM32_CECSW | STM32_I2C1SW |
+ RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLSRC |
+ STM32_ADCPRE | STM32_PPRE | STM32_HPRE;
+ RCC->CFGR2 = STM32_PREDIV;
+ RCC->CFGR3 = STM32_ADCSW | STM32_CECSW | STM32_I2C1SW |
STM32_USART1SW;
#if STM32_ACTIVATE_PLL
|