git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3481 35acf78f-673a-0410-8e92-d51de3d6d3f4

12 files changed, 274 insertions, 96 deletions

diff --git a/os/hal/platforms/STM32/can_lld.h b/os/hal/platforms/STM32/can_lld.h
index a9a086e5b..d99897935 100644
--- a/os/hal/platforms/STM32/can_lld.h
+++ b/os/hal/platforms/STM32/can_lld.h
@@ -75,6 +75,10 @@
 /*===========================================================================*/

 

 /**

+ * @name    Configuration options

+ * @{

+ */

+/**

  * @brief   CAN1 driver enable switch.

  * @details If set to @p TRUE the support for ADC1 is included.

  * @note    The default is @p TRUE.

@@ -89,6 +93,7 @@
 #if !defined(STM32_CAN_CAN1_IRQ_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_CAN_CAN1_IRQ_PRIORITY         11

 #endif

+/** @} */

 

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */

diff --git a/os/hal/platforms/STM32/ext_lld.h b/os/hal/platforms/STM32/ext_lld.h
index 753b12608..1a6102057 100644
--- a/os/hal/platforms/STM32/ext_lld.h
+++ b/os/hal/platforms/STM32/ext_lld.h
@@ -78,6 +78,10 @@
 /*===========================================================================*/

 

 /**

+ * @name    Configuration options

+ * @{

+ */

+/**

  * @brief   EXTI0 interrupt priority level setting.

  */

 #if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__)

@@ -174,6 +178,7 @@
 #if !defined(STM32_EXT_EXTI22_IRQ_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_EXT_EXTI22_IRQ_PRIORITY       6

 #endif

+/** @} */

 

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */

diff --git a/os/hal/platforms/STM32/gpt_lld.h b/os/hal/platforms/STM32/gpt_lld.h
index ef00c23a9..f61c5d030 100644
--- a/os/hal/platforms/STM32/gpt_lld.h
+++ b/os/hal/platforms/STM32/gpt_lld.h
@@ -40,6 +40,10 @@
 /*===========================================================================*/

 

 /**

+ * @name    Configuration options

+ * @{

+ */

+/**

  * @brief   GPTD1 driver enable switch.

  * @details If set to @p TRUE the support for GPTD1 is included.

  * @note    The default is @p TRUE.

@@ -134,6 +138,7 @@
 #if !defined(STM32_GPT_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_GPT_TIM8_IRQ_PRIORITY         7

 #endif

+/** @} */

 

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */

diff --git a/os/hal/platforms/STM32/i2c_lld.h b/os/hal/platforms/STM32/i2c_lld.h
index b66ba5d6a..81a9f62dc 100644
--- a/os/hal/platforms/STM32/i2c_lld.h
+++ b/os/hal/platforms/STM32/i2c_lld.h
@@ -37,6 +37,11 @@
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
 /*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
 /**
  * @brief Switch between callback based and synchronouse driver.
  * @note  The default is synchronouse.
@@ -98,6 +103,7 @@
 #if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__)
 #define STM32_I2C_I2C2_IRQ_PRIORITY     0xA0
 #endif
+/** @} */
 
 /*===========================================================================*/
 /* Derived constants and error checks.                                       */
diff --git a/os/hal/platforms/STM32/icu_lld.h b/os/hal/platforms/STM32/icu_lld.h
index 4c440b868..3156023eb 100644
--- a/os/hal/platforms/STM32/icu_lld.h
+++ b/os/hal/platforms/STM32/icu_lld.h
@@ -40,6 +40,10 @@
 /*===========================================================================*/

 

 /**

+ * @name    Configuration options

+ * @{

+ */

+/**

  * @brief   ICUD1 driver enable switch.

  * @details If set to @p TRUE the support for ICUD1 is included.

  * @note    The default is @p TRUE.

@@ -134,6 +138,7 @@
 #if !defined(STM32_ICU_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_ICU_TIM8_IRQ_PRIORITY         7

 #endif

+/** @} */

 

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */

diff --git a/os/hal/platforms/STM32/mac_lld.h b/os/hal/platforms/STM32/mac_lld.h
index 3e00639cc..d6eb4bfc4 100644
--- a/os/hal/platforms/STM32/mac_lld.h
+++ b/os/hal/platforms/STM32/mac_lld.h
@@ -115,6 +115,10 @@
 /*===========================================================================*/

 

 /**

+ * @name    Configuration options

+ * @{

+ */

+/**

  * @brief   Number of available transmit buffers.

  */

 #if !defined(MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__)

@@ -134,6 +138,7 @@
 #if !defined(MAC_BUFFERS_SIZE) || defined(__DOXYGEN__)

 #define MAC_BUFFERS_SIZE            1518

 #endif

+/** @} */

 

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */

diff --git a/os/hal/platforms/STM32/pwm_lld.h b/os/hal/platforms/STM32/pwm_lld.h
index d084b3dc7..78e411592 100644
--- a/os/hal/platforms/STM32/pwm_lld.h
+++ b/os/hal/platforms/STM32/pwm_lld.h
@@ -75,6 +75,10 @@
 /*===========================================================================*/

 

 /**

+ * @name    Configuration options

+ * @{

+ */

+/**

  * @brief   If advanced timer features switch.

  * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are

  *          enabled.

@@ -179,6 +183,7 @@
 #if !defined(STM32_PWM_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_PWM_TIM8_IRQ_PRIORITY         7

 #endif

+/** @} */

 

 /*===========================================================================*/

 /* Configuration checks.                                                     */

diff --git a/os/hal/platforms/STM32/sdc_lld.h b/os/hal/platforms/STM32/sdc_lld.h
index eea76dadd..f670e6bbe 100644
--- a/os/hal/platforms/STM32/sdc_lld.h
+++ b/os/hal/platforms/STM32/sdc_lld.h
@@ -41,6 +41,10 @@
 /*===========================================================================*/

 

 /**

+ * @name    Configuration options

+ * @{

+ */

+/**

  * @brief   SDIO data timeout in SDIO clock cycles.

  */

 #if !defined(STM32_SDC_DATATIMEOUT) || defined(__DOXYGEN__)

@@ -67,6 +71,7 @@
 #if !defined(STM32_SDC_UNALIGNED_SUPPORT) || defined(__DOXYGEN__)

 #define STM32_SDC_UNALIGNED_SUPPORT         TRUE

 #endif

+/** @} */

 

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */

diff --git a/os/hal/platforms/STM32/serial_lld.h b/os/hal/platforms/STM32/serial_lld.h
index fdd168201..ccafe736a 100644
--- a/os/hal/platforms/STM32/serial_lld.h
+++ b/os/hal/platforms/STM32/serial_lld.h
@@ -40,6 +40,10 @@
 /*===========================================================================*/

 

 /**

+ * @name    Configuration options

+ * @{

+ */

+/**

  * @brief   USART1 driver enable switch.

  * @details If set to @p TRUE the support for USART1 is included.

  * @note    The default is @p TRUE.

@@ -134,6 +138,7 @@
 #if !defined(STM32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_SERIAL_USART6_PRIORITY        12

 #endif

+/** @} */

 

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */

diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c
index f8ec8546c..1511547d5 100644
--- a/os/hal/platforms/STM32/spi_lld.c
+++ b/os/hal/platforms/STM32/spi_lld.c
@@ -32,6 +32,34 @@
 #if HAL_USE_SPI || defined(__DOXYGEN__)

 

 /*===========================================================================*/

+/* Driver local definitions.                                                 */

+/*===========================================================================*/

+

+#define SPI1_RX_DMA_CHANNEL                                                 \

+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_RX_DMA_STREAM,                        \

+                       STM32_SPI1_RX_DMA_CHN)

+

+#define SPI1_TX_DMA_CHANNEL                                                 \

+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_TX_DMA_STREAM,                        \

+                       STM32_SPI1_TX_DMA_CHN)

+

+#define SPI2_RX_DMA_CHANNEL                                                 \

+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_RX_DMA_STREAM,                        \

+                       STM32_SPI2_RX_DMA_CHN)

+

+#define SPI2_TX_DMA_CHANNEL                                                 \

+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_TX_DMA_STREAM,                        \

+                       STM32_SPI2_TX_DMA_CHN)

+

+#define SPI3_RX_DMA_CHANNEL                                                 \

+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_RX_DMA_STREAM,                        \

+                       STM32_SPI3_RX_DMA_CHN)

+

+#define SPI3_TX_DMA_CHANNEL                                                 \

+  STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_TX_DMA_STREAM,                        \

+                       STM32_SPI3_TX_DMA_CHN)

+

+/*===========================================================================*/

 /* Driver exported variables.                                                */

 /*===========================================================================*/

 

@@ -62,26 +90,6 @@ static uint16_t dummyrx;
 /*===========================================================================*/

 

 /**

- * @brief   Stops the SPI DMA channels.

- *

- * @param[in] spip      pointer to the @p SPIDriver object

- */

-#define dma_stop(spip) {                                                    \

-  dmaStreamDisable(spip->dmatx);                                            \

-  dmaStreamDisable(spip->dmarx);                                            \

-}

-

-/**

- * @brief   Starts the SPI DMA channels.

- *

- * @param[in] spip      pointer to the @p SPIDriver object

- */

-#define dma_start(spip) {                                                   \

-  dmaChannelEnable((spip)->dmarx);                                          \

-  dmaChannelEnable((spip)->dmatx);                                          \

-}

-

-/**

  * @brief   Shared end-of-rx service routine.

  *

  * @param[in] spip      pointer to the @p SPIDriver object

@@ -99,7 +107,8 @@ static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) {
 #endif

 

   /* Stop everything.*/

-  dma_stop(spip);

+  dmaStreamDisable(spip->dmatx);

+  dmaStreamDisable(spip->dmarx);

 

   /* Portable SPI ISR code defined in the high level driver, note, it is

      a macro.*/

@@ -145,26 +154,50 @@ void spi_lld_init(void) {
 

 #if STM32_SPI_USE_SPI1

   spiObjectInit(&SPID1);

-  SPID1.thread  = NULL;

-  SPID1.spi     = SPI1;

-  SPID1.dmarx   = STM32_DMA1_STREAM2;

-  SPID1.dmatx   = STM32_DMA1_STREAM3;

+  SPID1.spi       = SPI1;

+  SPID1.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM);

+  SPID1.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM);

+  SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) |

+                    STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |

+                    STM32_DMA_CR_DIR_P2M |

+                    STM32_DMA_CR_TCIE |

+                    STM32_DMA_CR_TEIE;

+  SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) |

+                    STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |

+                    STM32_DMA_CR_DIR_M2P |

+                    STM32_DMA_CR_TEIE;

 #endif

 

 #if STM32_SPI_USE_SPI2

   spiObjectInit(&SPID2);

-  SPID2.thread  = NULL;

-  SPID2.spi     = SPI2;

-  SPID2.dmarx   = STM32_DMA1_STREAM4;

-  SPID2.dmatx   = STM32_DMA1_STREAM5;

+  SPID2.spi       = SPI2;

+  SPID2.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM);

+  SPID2.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM);

+  SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) |

+                    STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |

+                    STM32_DMA_CR_DIR_P2M |

+                    STM32_DMA_CR_TCIE |

+                    STM32_DMA_CR_TEIE;

+  SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) |

+                    STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |

+                    STM32_DMA_CR_DIR_M2P |

+                    STM32_DMA_CR_TEIE;

 #endif

 

 #if STM32_SPI_USE_SPI3

   spiObjectInit(&SPID3);

-  SPID3.thread  = NULL;

-  SPID3.spi     = SPI3;

-  SPID3.dmarx   = STM32_DMA2_STREAM1;

-  SPID3.dmatx   = STM32_DMA2_STREAM2;

+  SPID3.spi       = SPI3;

+  SPID3.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM);

+  SPID3.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM);

+  SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) |

+                    STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |

+                    STM32_DMA_CR_DIR_P2M |

+                    STM32_DMA_CR_TCIE |

+                    STM32_DMA_CR_TEIE;

+  SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) |

+                    STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |

+                    STM32_DMA_CR_DIR_M2P |

+                    STM32_DMA_CR_TEIE;

 #endif

 }

 

@@ -182,12 +215,12 @@ void spi_lld_start(SPIDriver *spip) {
 #if STM32_SPI_USE_SPI1

     if (&SPID1 == spip) {

       bool_t b;

-      b = dmaStreamAllocate(STM32_DMA1_STREAM2,

+      b = dmaStreamAllocate(spip->dmarx,

                             STM32_SPI_SPI1_IRQ_PRIORITY,

                             (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,

                             (void *)spip);

       chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated");

-      b = dmaStreamAllocate(STM32_DMA1_STREAM3,

+      b = dmaStreamAllocate(spip->dmatx,

                             STM32_SPI_SPI1_IRQ_PRIORITY,

                             (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,

                             (void *)spip);

@@ -198,12 +231,12 @@ void spi_lld_start(SPIDriver *spip) {
 #if STM32_SPI_USE_SPI2

     if (&SPID2 == spip) {

       bool_t b;

-      b = dmaStreamAllocate(STM32_DMA1_STREAM4,

+      b = dmaStreamAllocate(spip->dmarx,

                             STM32_SPI_SPI2_IRQ_PRIORITY,

                             (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,

                             (void *)spip);

       chDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated");

-      b = dmaStreamAllocate(STM32_DMA1_STREAM5,

+      b = dmaStreamAllocate(spip->dmatx,

                             STM32_SPI_SPI2_IRQ_PRIORITY,

                             (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,

                             (void *)spip);

@@ -214,12 +247,12 @@ void spi_lld_start(SPIDriver *spip) {
 #if STM32_SPI_USE_SPI3

     if (&SPID3 == spip) {

       bool_t b;

-      b = dmaStreamAllocate(STM32_DMA2_STREAM1,

+      b = dmaStreamAllocate(spip->dmarx,

                             STM32_SPI_SPI3_IRQ_PRIORITY,

                             (stm32_dmaisr_t)spi_lld_serve_rx_interrupt,

                             (void *)spip);

       chDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated");

-      b = dmaStreamAllocate(STM32_DMA2_STREAM2,

+      b = dmaStreamAllocate(spip->dmatx,

                             STM32_SPI_SPI3_IRQ_PRIORITY,

                             (stm32_dmaisr_t)spi_lld_serve_tx_interrupt,

                             (void *)spip);

@@ -233,18 +266,19 @@ void spi_lld_start(SPIDriver *spip) {
     dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR);

   }

 

-  /* More DMA setup.*/

-  if ((spip->config->cr1 & SPI_CR1_DFF) == 0)

-    spip->dmamode = STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |

-                    STM32_DMA_CR_TEIE |

-                    STM32_DMA_CR_PSIZE_BYTE |

-                    STM32_DMA_CR_MSIZE_BYTE;        /* 8 bits transfers.    */

-  else

-    spip->dmamode = STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |

-                    STM32_DMA_CR_TEIE |

-                    STM32_DMA_CR_PSIZE_HWORD |

-                    STM32_DMA_CR_MSIZE_HWORD;       /* 16 bits transfers.   */

-

+  /* Configuration-specific DMA setup.*/

+  if ((spip->config->cr1 & SPI_CR1_DFF) == 0) {     /* 8 bits transfers.    */

+    spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |

+                      STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;

+    spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |

+                      STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;

+  }

+  else {                                            /* 16 bits transfers.   */

+    spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |

+                      STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;

+    spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |

+                      STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;

+  }

   /* SPI setup and enable.*/

   spip->spi->CR1  = 0;

   spip->spi->CR1  = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM |

@@ -267,27 +301,20 @@ void spi_lld_stop(SPIDriver *spip) {
 

     /* SPI disable.*/

     spip->spi->CR1 = 0;

+    dmaStreamRelease(spip->dmarx);

+    dmaStreamRelease(spip->dmatx);

 

 #if STM32_SPI_USE_SPI1

-    if (&SPID1 == spip) {

-      dmaStreamRelease(STM32_DMA1_STREAM2);

-      dmaStreamRelease(STM32_DMA1_STREAM3);

+    if (&SPID1 == spip)

       rccDisableSPI1(FALSE);

-    }

 #endif

 #if STM32_SPI_USE_SPI2

-    if (&SPID2 == spip) {

-      dmaStreamRelease(STM32_DMA1_STREAM4);

-      dmaStreamRelease(STM32_DMA1_STREAM5);

+    if (&SPID2 == spip)

       rccDisableSPI2(FALSE);

-    }

 #endif

 #if STM32_SPI_USE_SPI3

-    if (&SPID3 == spip) {

-      dmaStreamRelease(STM32_DMA2_STREAM1);

-      dmaStreamRelease(STM32_DMA2_STREAM2);

+    if (&SPID3 == spip)

       rccDisableSPI3(FALSE);

-    }

 #endif

   }

 }

@@ -332,12 +359,10 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) {
 

   dmaStreamSetMemory0(spip->dmarx, &dummyrx);

   dmaStreamSetTransactionSize(spip->dmarx, n);

-  dmaStreamSetMode(spip->dmarx, spip->dmamode | STM32_DMA_CR_DIR_P2M |

-                                STM32_DMA_CR_TCIE | STM32_DMA_CR_EN);

+  dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_EN);

   dmaStreamSetMemory0(spip->dmatx, &dummytx);

   dmaStreamSetTransactionSize(spip->dmatx, n);

-  dmaStreamSetMode(spip->dmatx, spip->dmamode | STM32_DMA_CR_DIR_M2P |

-                                STM32_DMA_CR_EN);

+  dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_EN);

 }

 

 /**

@@ -360,13 +385,12 @@ void spi_lld_exchange(SPIDriver *spip, size_t n,
 

   dmaStreamSetMemory0(spip->dmarx, rxbuf);

   dmaStreamSetTransactionSize(spip->dmarx, n);

-  dmaStreamSetMode(spip->dmarx, spip->dmamode | STM32_DMA_CR_DIR_P2M |

-                                STM32_DMA_CR_TCIE | STM32_DMA_CR_MINC |

-                                STM32_DMA_CR_EN);

+  dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC |

+                                                 STM32_DMA_CR_EN);

   dmaStreamSetMemory0(spip->dmatx, txbuf);

   dmaStreamSetTransactionSize(spip->dmatx, n);

-  dmaStreamSetMode(spip->dmatx, spip->dmamode | STM32_DMA_CR_DIR_M2P |

-                                STM32_DMA_CR_MINC | STM32_DMA_CR_EN);

+  dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC |

+                                                  STM32_DMA_CR_EN);

 }

 

 /**

@@ -386,12 +410,11 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
 

   dmaStreamSetMemory0(spip->dmarx, &dummyrx);

   dmaStreamSetTransactionSize(spip->dmarx, n);

-  dmaStreamSetMode(spip->dmarx, spip->dmamode | STM32_DMA_CR_DIR_P2M |

-                                STM32_DMA_CR_TCIE | STM32_DMA_CR_EN);

+  dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_EN);

   dmaStreamSetMemory0(spip->dmatx, txbuf);

   dmaStreamSetTransactionSize(spip->dmatx, n);

-  dmaStreamSetMode(spip->dmatx, spip->dmamode | STM32_DMA_CR_DIR_M2P |

-                                STM32_DMA_CR_MINC | STM32_DMA_CR_EN);

+  dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC |

+                                                  STM32_DMA_CR_EN);

 }

 

 /**

@@ -411,13 +434,11 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
 

   dmaStreamSetMemory0(spip->dmarx, rxbuf);

   dmaStreamSetTransactionSize(spip->dmarx, n);

-  dmaStreamSetMode(spip->dmarx, spip->dmamode | STM32_DMA_CR_DIR_P2M |

-                                STM32_DMA_CR_TCIE | STM32_DMA_CR_MINC |

-                                STM32_DMA_CR_EN);

+  dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC |

+                                                  STM32_DMA_CR_EN);

   dmaStreamSetMemory0(spip->dmatx, &dummytx);

   dmaStreamSetTransactionSize(spip->dmatx, n);

-  dmaStreamSetMode(spip->dmatx, spip->dmamode | STM32_DMA_CR_DIR_M2P |

-                                STM32_DMA_CR_EN);

+  dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_EN);

 }

 

 /**

diff --git a/os/hal/platforms/STM32/spi_lld.h b/os/hal/platforms/STM32/spi_lld.h
index c8c1e0661..5f4fd9224 100644
--- a/os/hal/platforms/STM32/spi_lld.h
+++ b/os/hal/platforms/STM32/spi_lld.h
@@ -40,6 +40,10 @@
 /*===========================================================================*/

 

 /**

+ * @name    Configuration options

+ * @{

+ */

+/**

  * @brief   SPI1 driver enable switch.

  * @details If set to @p TRUE the support for SPI1 is included.

  * @note    The default is @p TRUE.

@@ -68,9 +72,9 @@
 

 /**

  * @brief   SPI1 DMA priority (0..3|lowest..highest).

- * @note    The priority level is used for both the TX and RX DMA channels but

- *          because of the channels ordering the RX channel has always priority

- *          over the TX channel.

+ * @note    The priority level is used for both the TX and RX DMA streams but

+ *          because of the streams ordering the RX stream has always priority

+ *          over the TX stream.

  */

 #if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_SPI_SPI1_DMA_PRIORITY         1

@@ -78,9 +82,9 @@
 

 /**

  * @brief   SPI2 DMA priority (0..3|lowest..highest).

- * @note    The priority level is used for both the TX and RX DMA channels but

- *          because of the channels ordering the RX channel has always priority

- *          over the TX channel.

+ * @note    The priority level is used for both the TX and RX DMA streams but

+ *          because of the streams ordering the RX stream has always priority

+ *          over the TX stream.

  */

 #if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_SPI_SPI2_DMA_PRIORITY         1

@@ -88,9 +92,9 @@
 

 /**

  * @brief   SPI3 DMA priority (0..3|lowest..highest).

- * @note    The priority level is used for both the TX and RX DMA channels but

- *          because of the channels ordering the RX channel has always priority

- *          over the TX channel.

+ * @note    The priority level is used for both the TX and RX DMA streams but

+ *          because of the streams ordering the RX stream has always priority

+ *          over the TX stream.

  */

 #if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_SPI_SPI3_DMA_PRIORITY         1

@@ -119,13 +123,64 @@
 

 /**

  * @brief   SPI DMA error hook.

- * @note    The default action for DMA errors is a system halt because DMA

- *          error can only happen because programming errors.

  */

 #if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)

 #define STM32_SPI_DMA_ERROR_HOOK(spip)      chSysHalt()

 #endif

 

+#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)

+

+/**

+ * @brief   DMA stream used for SPI1 RX operations.

+ * @note    This option is only available on platforms with enhanced DMA.

+ */

+#if !defined(STM32_SPI_SPI1_RX_DMA_STREAM) || defined(__DOXYGEN__)

+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)

+#endif

+

+/**

+ * @brief   DMA stream used for SPI1 TX operations.

+ * @note    This option is only available on platforms with enhanced DMA.

+ */

+#if !defined(STM32_SPI_SPI1_TX_DMA_STREAM) || defined(__DOXYGEN__)

+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)

+#endif

+

+/**

+ * @brief   DMA stream used for SPI2 RX operations.

+ * @note    This option is only available on platforms with enhanced DMA.

+ */

+#if !defined(STM32_SPI_SPI2_RX_DMA_STREAM) || defined(__DOXYGEN__)

+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)

+#endif

+

+/**

+ * @brief   DMA stream used for SPI2 TX operations.

+ * @note    This option is only available on platforms with enhanced DMA.

+ */

+#if !defined(STM32_SPI_SPI2_TX_DMA_STREAM) || defined(__DOXYGEN__)

+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

+#endif

+

+/**

+ * @brief   DMA stream used for SPI3 RX operations.

+ * @note    This option is only available on platforms with enhanced DMA.

+ */

+#if !defined(STM32_SPI_SPI3_RX_DMA_STREAM) || defined(__DOXYGEN__)

+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)

+#endif

+

+/**

+ * @brief   DMA stream used for SPI3 TX operations.

+ * @note    This option is only available on platforms with enhanced DMA.

+ */

+#if !defined(STM32_SPI_SPI3_TX_DMA_STREAM) || defined(__DOXYGEN__)

+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)

+#endif

+

+#endif /* STM32_ADVANCED_DMA*/

+/** @} */

+

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

@@ -146,6 +201,53 @@
 #error "SPI driver activated but no SPI peripheral assigned"

 #endif

 

+#if STM32_ADVANCED_DMA

+

+/* Checks to be performed only on platforms using the advanced DMA

+   peripheral.*/

+#if STM32_SPI_USE_SPI1 &&                                                   \

+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK)

+#error "invalid DMA stream associated to SPI1 RX"

+#endif

+

+#if STM32_SPI_USE_SPI1 &&                                                   \

+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK)

+#error "invalid DMA stream associated to SPI1 TX"

+#endif

+

+#if STM32_SPI_USE_SPI2 &&                                                   \

+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK)

+#error "invalid DMA stream associated to SPI2 RX"

+#endif

+

+#if STM32_SPI_USE_SPI2 &&                                                   \

+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK)

+#error "invalid DMA stream associated to SPI2 TX"

+#endif

+

+#if STM32_SPI_USE_SPI3 &&                                                   \

+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK)

+#error "invalid DMA stream associated to SPI3 RX"

+#endif

+

+#if STM32_SPI_USE_SPI3 &&                                                   \

+    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK)

+#error "invalid DMA stream associated to SPI3 TX"

+#endif

+

+#else /* !STM32_ADVANCED_DMA */

+

+/* Fixed streams for platforms using the old DMA peripheral, the values are

+   valid for both STM32F1xx and STM32L1xx.*/

+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)

+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)

+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)

+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 5)

+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 6)

+

+#endif /* !STM32_ADVANCED_DMA */

+

 #if !defined(STM32_DMA_REQUIRED)

 #define STM32_DMA_REQUIRED

 #endif

@@ -227,17 +329,21 @@ struct SPIDriver{
    */

   SPI_TypeDef               *spi;

   /**

-   * @brief Receive DMA channel.

+   * @brief Receive DMA stream.

    */

   const stm32_dma_stream_t  *dmarx;

   /**

-   * @brief Transmit DMA channel.

+   * @brief Transmit DMA stream.

    */

   const stm32_dma_stream_t  *dmatx;

   /**

-   * @brief DMA mode bit mask.

+   * @brief RX DMA mode bit mask.

+   */

+  uint32_t                  rxdmamode;

+  /**

+   * @brief TX DMA mode bit mask.

    */

-  uint32_t                  dmamode;

+  uint32_t                  txdmamode;

 };

 

 /*===========================================================================*/

diff --git a/os/hal/platforms/STM32/uart_lld.h b/os/hal/platforms/STM32/uart_lld.h
index aff7f52ba..d97bea91b 100644
--- a/os/hal/platforms/STM32/uart_lld.h
+++ b/os/hal/platforms/STM32/uart_lld.h
@@ -40,6 +40,10 @@
 /*===========================================================================*/

 

 /**

+ * @name    Configuration options

+ * @{

+ */

+/**

  * @brief   UART driver on USART1 enable switch.

  * @details If set to @p TRUE the support for USART1 is included.

  * @note    The default is @p FALSE.

@@ -124,6 +128,7 @@
 #if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__)

 #define STM32_UART_DMA_ERROR_HOOK(uartp)    chSysHalt()

 #endif

+/** @} */

 

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */