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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2013-04-06 11:31:05 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2013-04-06 11:31:05 +0000
commit03fab93a8b8809ac405e83349579fbfa8adfb7f0 (patch)
tree2a7f1b6d8e9b0a3f63caf63a3bf9063b67ed5e87 /os/hal/platforms/STM32
parent44a4c3aacb6bc9ea440ca4a74cb3d568051f1317 (diff)
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STM32 I2Cv2 driver now working correctly.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5548 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32')
-rw-r--r--os/hal/platforms/STM32/I2Cv2/i2c_lld.c36
1 files changed, 18 insertions, 18 deletions
diff --git a/os/hal/platforms/STM32/I2Cv2/i2c_lld.c b/os/hal/platforms/STM32/I2Cv2/i2c_lld.c
index dd20758cc..3a6c8f7f8 100644
--- a/os/hal/platforms/STM32/I2Cv2/i2c_lld.c
+++ b/os/hal/platforms/STM32/I2Cv2/i2c_lld.c
@@ -624,6 +624,15 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
/* Releases the lock from high level driver.*/
chSysUnlock();
+ /* Waits until BUSY flag is reset and the STOP from the previous operation
+ is completed, alternatively for a timeout condition.*/
+ while (dp->ISR & I2C_ISR_BUSY) {
+ chSysLock();
+ if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
+ return RDY_TIMEOUT;
+ chSysUnlock();
+ }
+
/* Adjust slave address (master mode) for 7-bit address mode */
if ((i2cp->config->cr2 & I2C_CR2_ADD10) == 0)
addr_cr2 = (addr_cr2 & 0x7f) << 1;
@@ -643,15 +652,6 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
/* Enable RX DMA */
dmaStreamEnable(i2cp->dmarx);
- /* Waits until BUSY flag is reset and the STOP from the previous operation
- is completed, alternatively for a timeout condition.*/
- while (dp->ISR & I2C_ISR_BUSY) {
- chSysLock();
- if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
- return RDY_TIMEOUT;
- chSysUnlock();
- }
-
/* This lock will be released in high level driver.*/
chSysLock();
@@ -719,6 +719,15 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
/* Releases the lock from high level driver.*/
chSysUnlock();
+ /* Waits until BUSY flag is reset and the STOP from the previous operation
+ is completed, alternatively for a timeout condition.*/
+ while (dp->ISR & I2C_ISR_BUSY) {
+ chSysLock();
+ if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
+ return RDY_TIMEOUT;
+ chSysUnlock();
+ }
+
/* Adjust slave address (master mode) for 7-bit address mode */
if ((i2cp->config->cr2 & I2C_CR2_ADD10) == 0)
addr_cr2 = (addr_cr2 & 0x7f) << 1;
@@ -743,15 +752,6 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
/* Enable TX DMA */
dmaStreamEnable(i2cp->dmatx);
- /* Waits until BUSY flag is reset and the STOP from the previous operation
- is completed, alternatively for a timeout condition.*/
- while (dp->ISR & I2C_ISR_BUSY) {
- chSysLock();
- if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
- return RDY_TIMEOUT;
- chSysUnlock();
- }
-
/* This lock will be released in high level driver.*/
chSysLock();