Fixed bug 3041414. Various improvements to the STM32 HAL.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2119 35acf78f-673a-0410-8e92-d51de3d6d3f4

1 files changed, 30 insertions, 30 deletions

diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c
index 95501626c..31e2f097a 100644
--- a/os/hal/platforms/STM32/spi_lld.c
+++ b/os/hal/platforms/STM32/spi_lld.c
@@ -35,17 +35,17 @@
 /*===========================================================================*/

 

 /** @brief SPI1 driver identifier.*/

-#if USE_STM32_SPI1 || defined(__DOXYGEN__)

+#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__)

 SPIDriver SPID1;

 #endif

 

 /** @brief SPI2 driver identifier.*/

-#if USE_STM32_SPI2 || defined(__DOXYGEN__)

+#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__)

 SPIDriver SPID2;

 #endif

 

 /** @brief SPI3 driver identifier.*/

-#if USE_STM32_SPI3 || defined(__DOXYGEN__)

+#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__)

 SPIDriver SPID3;

 #endif

 

@@ -112,7 +112,7 @@ static void spi_start_wait(SPIDriver *spip, size_t n,
 /* Driver interrupt handlers.                                                */

 /*===========================================================================*/

 

-#if USE_STM32_SPI1 || defined(__DOXYGEN__)

+#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__)

 /**

  * @brief   SPI1 RX DMA interrupt handler (channel 2).

  */

@@ -122,7 +122,7 @@ CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) {
 

   spi_stop(&SPID1);

   if ((DMA1->ISR & DMA_ISR_TEIF2) != 0) {

-    STM32_SPI1_DMA_ERROR_HOOK();

+    STM32_SPI_SPI1_DMA_ERROR_HOOK();

   }

   DMA1->IFCR = DMA_IFCR_CGIF2  | DMA_IFCR_CTCIF2 |

                DMA_IFCR_CHTIF2 | DMA_IFCR_CTEIF2;

@@ -137,7 +137,7 @@ CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) {
 

   CH_IRQ_PROLOGUE();

 

-  STM32_SPI1_DMA_ERROR_HOOK();

+  STM32_SPI_SPI1_DMA_ERROR_HOOK();

   DMA1->IFCR = DMA_IFCR_CGIF3  | DMA_IFCR_CTCIF3 |

                DMA_IFCR_CHTIF3 | DMA_IFCR_CTEIF3;

 

@@ -145,7 +145,7 @@ CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) {
 }

 #endif

 

-#if USE_STM32_SPI2 || defined(__DOXYGEN__)

+#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__)

 /**

  * @brief   SPI2 RX DMA interrupt handler (channel 4).

  */

@@ -155,7 +155,7 @@ CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) {
 

   spi_stop(&SPID2);

   if ((DMA1->ISR & DMA_ISR_TEIF4) != 0) {

-    STM32_SPI2_DMA_ERROR_HOOK();

+    STM32_SPI_SPI2_DMA_ERROR_HOOK();

   }

   DMA1->IFCR = DMA_IFCR_CGIF4  | DMA_IFCR_CTCIF4 |

                DMA_IFCR_CHTIF4 | DMA_IFCR_CTEIF4;

@@ -170,7 +170,7 @@ CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) {
 

   CH_IRQ_PROLOGUE();

 

-  STM32_SPI2_DMA_ERROR_HOOK();

+  STM32_SPI_SPI2_DMA_ERROR_HOOK();

   DMA1->IFCR = DMA_IFCR_CGIF5  | DMA_IFCR_CTCIF5 |

                DMA_IFCR_CHTIF5 | DMA_IFCR_CTEIF5;

 

@@ -178,7 +178,7 @@ CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) {
 }

 #endif

 

-#if USE_STM32_SPI3 || defined(__DOXYGEN__)

+#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__)

 /**

  * @brief   SPI3 RX DMA interrupt handler (DMA2, channel 1).

  */

@@ -188,7 +188,7 @@ CH_IRQ_HANDLER(DMA2_Ch1_IRQHandler) {
 

   spi_stop(&SPID3);

   if ((DMA2->ISR & DMA_ISR_TEIF1) != 0) {

-    STM32_SPI3_DMA_ERROR_HOOK();

+    STM32_SPI_SPI3_DMA_ERROR_HOOK();

   }

   DMA2->IFCR = DMA_IFCR_CGIF1  | DMA_IFCR_CTCIF1 |

                DMA_IFCR_CHTIF1 | DMA_IFCR_CTEIF1;

@@ -203,7 +203,7 @@ CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) {
 

   CH_IRQ_PROLOGUE();

 

-  STM32_SPI3_DMA_ERROR_HOOK();

+  STM32_SPI_SPI3_DMA_ERROR_HOOK();

   DMA2->IFCR = DMA_IFCR_CGIF2  | DMA_IFCR_CTCIF2 |

                DMA_IFCR_CHTIF2 | DMA_IFCR_CTEIF2;

 

@@ -222,7 +222,7 @@ void spi_lld_init(void) {
 

   dummytx = 0xFFFF;

 

-#if USE_STM32_SPI1

+#if STM32_SPI_USE_SPI1

   RCC->APB2RSTR     = RCC_APB2RSTR_SPI1RST;

   RCC->APB2RSTR     = 0;

   spiObjectInit(&SPID1);

@@ -230,10 +230,10 @@ void spi_lld_init(void) {
   SPID1.spd_spi     = SPI1;

   SPID1.spd_dmarx   = DMA1_Channel2;

   SPID1.spd_dmatx   = DMA1_Channel3;

-  SPID1.spd_dmaprio = STM32_SPI1_DMA_PRIORITY << 12;

+  SPID1.spd_dmaprio = STM32_SPI_SPI1_DMA_PRIORITY << 12;

 #endif

 

-#if USE_STM32_SPI2

+#if STM32_SPI_USE_SPI2

   RCC->APB1RSTR     = RCC_APB1RSTR_SPI2RST;

   RCC->APB1RSTR     = 0;

   spiObjectInit(&SPID2);

@@ -241,10 +241,10 @@ void spi_lld_init(void) {
   SPID2.spd_spi     = SPI2;

   SPID2.spd_dmarx   = DMA1_Channel4;

   SPID2.spd_dmatx   = DMA1_Channel5;

-  SPID2.spd_dmaprio = STM32_SPI2_DMA_PRIORITY << 12;

+  SPID2.spd_dmaprio = STM32_SPI_SPI2_DMA_PRIORITY << 12;

 #endif

 

-#if USE_STM32_SPI3

+#if STM32_SPI_USE_SPI3

   RCC->APB1RSTR     = RCC_APB1RSTR_SPI3RST;

   RCC->APB1RSTR     = 0;

   spiObjectInit(&SPID3);

@@ -252,7 +252,7 @@ void spi_lld_init(void) {
   SPID3.spd_spi     = SPI3;

   SPID3.spd_dmarx   = DMA2_Channel1;

   SPID3.spd_dmatx   = DMA2_Channel2;

-  SPID3.spd_dmaprio = STM32_SPI3_DMA_PRIORITY << 12;

+  SPID3.spd_dmaprio = STM32_SPI_SPI3_DMA_PRIORITY << 12;

 #endif

 }

 

@@ -265,33 +265,33 @@ void spi_lld_start(SPIDriver *spip) {
 

   /* If in stopped state then enables the SPI and DMA clocks.*/

   if (spip->spd_state == SPI_STOP) {

-#if USE_STM32_SPI1

+#if STM32_SPI_USE_SPI1

     if (&SPID1 == spip) {

       dmaEnable(DMA1_ID);   /* NOTE: Must be enabled before the IRQs.*/

       NVICEnableVector(DMA1_Channel2_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_SPI1_IRQ_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_SPI_SPI1_IRQ_PRIORITY));

       NVICEnableVector(DMA1_Channel3_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_SPI1_IRQ_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_SPI_SPI1_IRQ_PRIORITY));

       RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;

     }

 #endif

-#if USE_STM32_SPI2

+#if STM32_SPI_USE_SPI2

     if (&SPID2 == spip) {

       dmaEnable(DMA1_ID);   /* NOTE: Must be enabled before the IRQs.*/

       NVICEnableVector(DMA1_Channel4_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_SPI2_IRQ_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_SPI_SPI2_IRQ_PRIORITY));

       NVICEnableVector(DMA1_Channel5_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_SPI2_IRQ_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_SPI_SPI2_IRQ_PRIORITY));

       RCC->APB1ENR |= RCC_APB1ENR_SPI2EN;

     }

 #endif

-#if USE_STM32_SPI3

+#if STM32_SPI_USE_SPI3

     if (&SPID3 == spip) {

       dmaEnable(DMA2_ID);   /* NOTE: Must be enabled before the IRQs.*/

       NVICEnableVector(DMA2_Channel1_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_SPI3_IRQ_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_SPI_SPI3_IRQ_PRIORITY));

       NVICEnableVector(DMA2_Channel2_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_SPI3_IRQ_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_SPI_SPI3_IRQ_PRIORITY));

       RCC->APB1ENR |= RCC_APB1ENR_SPI3EN;

     }

 #endif

@@ -315,7 +315,7 @@ void spi_lld_stop(SPIDriver *spip) {
 

   /* If in ready state then disables the SPI clock.*/

   if (spip->spd_state == SPI_READY) {

-#if USE_STM32_SPI1

+#if STM32_SPI_USE_SPI1

     if (&SPID1 == spip) {

       NVICDisableVector(DMA1_Channel2_IRQn);

       NVICDisableVector(DMA1_Channel3_IRQn);

@@ -323,7 +323,7 @@ void spi_lld_stop(SPIDriver *spip) {
       RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN;

     }

 #endif

-#if USE_STM32_SPI2

+#if STM32_SPI_USE_SPI2

     if (&SPID2 == spip) {

       NVICDisableVector(DMA1_Channel4_IRQn);

       NVICDisableVector(DMA1_Channel5_IRQn);

@@ -331,7 +331,7 @@ void spi_lld_stop(SPIDriver *spip) {
       RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN;

     }

 #endif

-#if USE_STM32_SPI3

+#if STM32_SPI_USE_SPI3

     if (&SPID3 == spip) {

       NVICDisableVector(DMA2_Channel1_IRQn);

       NVICDisableVector(DMA2_Channel2_IRQn);