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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-03-30 17:04:51 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-03-30 17:04:51 +0000 |
| commit | 1134fe2a87e70cad601394793f0f01cfef066b70 (patch) | |
| tree | c9748d498a31a5cfc7bf6124319428d499da1cf1 /os/hal/platforms/STM32/serial_lld.h | |
| parent | 5fa5b9ef5616c00ed5ae936a2efadfba47bcaa1f (diff) | |
| download | ChibiOS-1134fe2a87e70cad601394793f0f01cfef066b70.tar.gz ChibiOS-1134fe2a87e70cad601394793f0f01cfef066b70.tar.bz2 ChibiOS-1134fe2a87e70cad601394793f0f01cfef066b70.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1814 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32/serial_lld.h')
| -rw-r--r-- | os/hal/platforms/STM32/serial_lld.h | 20 |
1 files changed, 5 insertions, 15 deletions
diff --git a/os/hal/platforms/STM32/serial_lld.h b/os/hal/platforms/STM32/serial_lld.h index eb625230b..861582d54 100644 --- a/os/hal/platforms/STM32/serial_lld.h +++ b/os/hal/platforms/STM32/serial_lld.h @@ -87,48 +87,38 @@ /**
* @brief USART1 interrupt priority level setting.
- * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_USART1_PRIORITY >
- * @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_USART1_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_USART1_PRIORITY CORTEX_PRIORITY(12)
+#define STM32_USART1_PRIORITY 12
#endif
/**
* @brief USART2 interrupt priority level setting.
- * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_USART2_PRIORITY >
- * @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_USART2_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_USART2_PRIORITY CORTEX_PRIORITY(12)
+#define STM32_USART2_PRIORITY 12)
#endif
/**
* @brief USART3 interrupt priority level setting.
- * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_USART3_PRIORITY >
- * @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_USART3_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_USART3_PRIORITY CORTEX_PRIORITY(12)
+#define STM32_USART3_PRIORITY 12
#endif
#if defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(__DOXYGEN__)
/**
* @brief UART4 interrupt priority level setting.
- * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_USART2_PRIORITY >
- * @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_UART4_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART4_PRIORITY CORTEX_PRIORITY(12)
+#define STM32_UART4_PRIORITY 12
#endif
/**
* @brief UART5 interrupt priority level setting.
- * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_USART2_PRIORITY >
- * @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_UART5_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART5_PRIORITY CORTEX_PRIORITY(12)
+#define STM32_UART5_PRIORITY 12
#endif
#endif
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