RTC. Code reorganization to correspond ChibiOS rules.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3356 35acf78f-673a-0410-8e92-d51de3d6d3f4

1 files changed, 20 insertions, 23 deletions

diff --git a/os/hal/platforms/STM32/rtc_lld.c b/os/hal/platforms/STM32/rtc_lld.c
index 941f2429f..465f2f02e 100644
--- a/os/hal/platforms/STM32/rtc_lld.c
+++ b/os/hal/platforms/STM32/rtc_lld.c
@@ -115,23 +115,14 @@ void rtc_lld_init(void){
   uint32_t preload = 0;

 

   rccEnableBKPInterface(FALSE);

-

-  /* Ensure that RTC_CNT and RTC_DIV contain actual values after enabling

-   * clocking on APB1, because these values only update when APB1 functioning.*/

-  RTC->CRL &= ~(RTC_CRL_RSF);

-  while (!(RTC->CRL & RTC_CRL_RSF))

-    ;

+  //RCC->APB1ENR |= (RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN);

 

   /* enable access to BKP registers */

   PWR->CR |= PWR_CR_DBP;

   /* select clock source */

-  RCC->BDCR |= RTC_CLOCK_SOURCE;

+  RCC->BDCR |= STM32_RTC;

 

-  chDbgCheck(((RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSE) &&\

-              (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSI) &&\

-              (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_HSE)), "No clock source selected");

-

-  if (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSE){

+#if STM32_RTC == STM32_RTC_LSE

     if (! ((RCC->BDCR & RCC_BDCR_RTCEN) || (RCC->BDCR & RCC_BDCR_LSEON))){

       RCC->BDCR |= RCC_BDCR_LSEON;

       while(!(RCC->BDCR & RCC_BDCR_LSERDY))

@@ -139,26 +130,32 @@ void rtc_lld_init(void){
       RCC->BDCR |= RCC_BDCR_RTCEN;

     }

     preload = STM32_LSECLK - 1;

-  }

-  else if (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_LSI){

+

+#elif STM32_RTC == STM32_RTC_LSI

     RCC->CSR  |= RCC_CSR_LSION;

     while(!(RCC->CSR & RCC_CSR_LSIRDY))

       ;

-    /* According to errata notes we must wait additional 100 uS for stabilization */

+    /* According to errata sheet we must wait additional 100 uS for stabilization */

     uint32_t tmo = (STM32_SYSCLK / 1000000 ) * 100;

     while(tmo--)

       ;

     RCC->BDCR |= RCC_BDCR_RTCEN;

     preload = STM32_LSICLK - 1;

-  }

-  else if (RTC_CLOCK_SOURCE == RCC_BDCR_RTCSEL_HSE){

+

+#elif STM32_RTC == STM32_RTC_HSE

     preload = (STM32_HSICLK / 128) - 1;

-  }

-  else{

-    chDbgPanic("Wrong");

-  }

 

-  /* Write preload register only if value changed */

+#else

+#error "RTC clock source not selected"

+#endif

+

+  /* Ensure that RTC_CNT and RTC_DIV contain actual values after enabling

+   * clocking on APB1, because these values only update when APB1 functioning.*/

+  RTC->CRL &= ~(RTC_CRL_RSF);

+  while (!(RTC->CRL & RTC_CRL_RSF))

+    ;

+

+  /* Write preload register only if its value changed */

   if (preload != ((((uint32_t)(RTC->PRLH)) << 16) + RTC->PRLL)){

     while(!(RTC->CRL & RTC_CRL_RTOFF))

       ;

@@ -174,7 +171,7 @@ void rtc_lld_init(void){
 

   /* disable all interrupts and clear all even flags just to be safe */

   RTC->CRH &= ~(RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE);

-  RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF);

+  RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF  | RTC_CRL_OWF);

 

 #if RTC_SUPPORTS_CALLBACKS

   RTCD.alarm_cb    = NULL;