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authorbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2011-12-01 20:17:58 +0000
committerbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2011-12-01 20:17:58 +0000
commit62608271adb730505a4a3d0a9ef49ef2efe91552 (patch)
tree55148b4aecb862b55ba943172faccecbec7b8c67 /os/hal/platforms/STM32/i2c_lld.h
parent750f1f4ae6ce75e0cbd8d6923b026376b607ffad (diff)
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I2C. Code compiles but does not work.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3548 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32/i2c_lld.h')
-rw-r--r--os/hal/platforms/STM32/i2c_lld.h53
1 files changed, 10 insertions, 43 deletions
diff --git a/os/hal/platforms/STM32/i2c_lld.h b/os/hal/platforms/STM32/i2c_lld.h
index 24195147a..e4fb8970f 100644
--- a/os/hal/platforms/STM32/i2c_lld.h
+++ b/os/hal/platforms/STM32/i2c_lld.h
@@ -42,33 +42,6 @@
* @name Configuration options
* @{
*/
-/**
- * @brief Switch between callback based and synchronouse driver.
- * @note The default is synchronouse.
- */
-#if !defined(I2C_SUPPORTS_CALLBACKS) || defined(__DOXYGEN__)
-#define I2C_SUPPORTS_CALLBACKS TRUE
-#endif
-
-/**
- * @brief I2C1 driver synchronization choice between GPT and polling.
- * @note The default is polling wait.
- */
-#if !defined(STM32_I2C_I2C1_USE_GPT_TIM) || \
- !defined(STM32_I2C_I2C1_USE_POLLING_WAIT) || \
- defined(__DOXYGEN__)
-#define STM32_I2C_I2C1_USE_POLLING_WAIT TRUE
-#endif
-
-/**
- * @brief I2C2 driver synchronization choice between GPT and polling.
- * @note The default is polling wait.
- */
-#if !defined(STM32_I2C_I2C2_USE_GPT_TIM) || \
- !defined(STM32_I2C_I2C2_USE_POLLING_WAIT) || \
- defined(__DOXYGEN__)
-#define STM32_I2C_I2C2_USE_POLLING_WAIT TRUE
-#endif
/**
* @brief I2C1 driver enable switch.
@@ -238,25 +211,22 @@ struct I2CDriver{
#endif
/*********** End of the mandatory fields. **********************************/
-
/**
- * @brief Pointer to the I2Cx registers block.
+ * @brief DMA mode bit mask.
*/
- I2C_TypeDef *id_i2c;
-
-#if !(STM32_I2C_I2C1_USE_POLLING_WAIT)
- /* TODO: capability to switch this GPT fields off */
+ uint32_t dmamode;
/**
- * @brief Timer for waiting STOP condition on the bus.
- * @details This is workaround for STM32 buggy I2C cell.
+ * @brief Receive DMA channel.
*/
- GPTDriver *timer;
-
+ const stm32_dma_stream_t *dmarx;
/**
- * @brief Config for workaround timer.
+ * @brief Transmit DMA channel.
*/
- const GPTConfig *timer_cfg;
-#endif /* !(STM32_I2C_I2C1_USE_POLLING_WAIT) */
+ const stm32_dma_stream_t *dmatx;
+ /**
+ * @brief Pointer to the I2Cx registers block.
+ */
+ I2C_TypeDef *id_i2c;
};
@@ -308,9 +278,6 @@ void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr,
uint8_t *rxbuf, size_t rxbytes);
void i2c_lld_master_transceive(I2CDriver *i2cp);
-void i2c_lld_master_transmit_dma(I2CDriver *i2cp, uint16_t slave_addr,
- uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes);
-
#ifdef __cplusplus
}
#endif