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| author | barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-01-02 19:04:50 +0000 |
|---|---|---|
| committer | barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-01-02 19:04:50 +0000 |
| commit | 86b3f07923ebbcff11950efc4d5b9a76f5b33710 (patch) | |
| tree | 882ce914d5e6fb8769b031257eabf9a766f8e0a0 /os/hal/platforms/STM32/i2c_lld.c | |
| parent | fc44d8dbc601e9fa20c8c32402944faf11fe67c2 (diff) | |
| download | ChibiOS-86b3f07923ebbcff11950efc4d5b9a76f5b33710.tar.gz ChibiOS-86b3f07923ebbcff11950efc4d5b9a76f5b33710.tar.bz2 ChibiOS-86b3f07923ebbcff11950efc4d5b9a76f5b33710.zip | |
I2C. Reorganized locks.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3711 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32/i2c_lld.c')
| -rw-r--r-- | os/hal/platforms/STM32/i2c_lld.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c index 352d213f8..51e41d4fe 100644 --- a/os/hal/platforms/STM32/i2c_lld.c +++ b/os/hal/platforms/STM32/i2c_lld.c @@ -666,7 +666,9 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); dmaStreamSetMode(i2cp->dmarx, ((i2cp->dmamode) | STM32_DMA_CR_DIR_P2M)); - i2c_lld_wait_bus_free(i2cp); + /* Wait until BUSY flag is reset. */ + while(i2cp->i2c->SR2 & I2C_SR2_BUSY) + ; /* wait stop bit from previous transaction*/ while(i2cp->i2c->CR1 & I2C_CR1_STOP) @@ -675,6 +677,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2cp->i2c->CR2 |= I2C_CR2_ITERREN | I2C_CR2_ITEVTEN; i2cp->i2c->CR1 |= I2C_CR1_START | I2C_CR1_ACK; + chSysLock(); /* this lock will be released in high level part */ i2c_lld_wait_s(i2cp, timeout, rdymsg); return rdymsg; @@ -724,7 +727,9 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, uint8_t slave_addr, dmaStreamSetTransactionSize(i2cp->dmatx, txbytes); dmaStreamSetMode(i2cp->dmatx, ((i2cp->dmamode) | STM32_DMA_CR_DIR_M2P)); - i2c_lld_wait_bus_free(i2cp); + /* Wait until BUSY flag is reset. */ + while(i2cp->i2c->SR2 & I2C_SR2_BUSY) + ; /* wait stop bit from previous transaction*/ while(i2cp->i2c->CR1 & I2C_CR1_STOP) @@ -733,6 +738,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, uint8_t slave_addr, i2cp->i2c->CR2 |= I2C_CR2_ITERREN | I2C_CR2_ITEVTEN; i2cp->i2c->CR1 |= I2C_CR1_START; + chSysLock(); /* this lock will be released in high level part */ i2c_lld_wait_s(i2cp, timeout, rdymsg); return rdymsg; |