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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2009-11-29 08:50:13 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2009-11-29 08:50:13 +0000 |
| commit | d4c616e6eeb0587ca450c75b1086efa77ac690e5 (patch) | |
| tree | 956be5c79924929b0c79c6aa792ad5b8bff31ede /os/hal/platforms/STM32/hal_lld.c | |
| parent | 87417b01023059aa833f376d9bd7aea5174a5f1b (diff) | |
| download | ChibiOS-d4c616e6eeb0587ca450c75b1086efa77ac690e5.tar.gz ChibiOS-d4c616e6eeb0587ca450c75b1086efa77ac690e5.tar.bz2 ChibiOS-d4c616e6eeb0587ca450c75b1086efa77ac690e5.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1351 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32/hal_lld.c')
| -rw-r--r-- | os/hal/platforms/STM32/hal_lld.c | 128 |
1 files changed, 128 insertions, 0 deletions
diff --git a/os/hal/platforms/STM32/hal_lld.c b/os/hal/platforms/STM32/hal_lld.c new file mode 100644 index 000000000..cce126c8e --- /dev/null +++ b/os/hal/platforms/STM32/hal_lld.c @@ -0,0 +1,128 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file STM32/hal_lld.c
+ * @brief STM32 HAL subsystem low level driver source
+ * @addtogroup STM32_HAL
+ * @{
+ */
+
+#include <ch.h>
+#include <hal.h>
+
+#define AIRCR_VECTKEY 0x05FA0000
+
+/*===========================================================================*/
+/* Low Level Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Low Level Driver local variables. */
+/*===========================================================================*/
+
+/*
+ * Digital I/O ports static configuration as defined in @p board.h.
+ */
+const STM32GPIOConfig pal_default_config =
+{
+ {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+ {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+ {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+ {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+#if !defined(STM32F10X_LD)
+ {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+#endif
+#if defined(STM32F10X_HD)
+ {VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH},
+ {VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH},
+#endif
+};
+
+/*===========================================================================*/
+/* Low Level Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Low Level Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Low Level Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ */
+void hal_lld_init(void) {
+
+#if CH_HAL_USE_ADC || CH_HAL_USE_SPI
+ dmaInit();
+#endif
+}
+
+/**
+ * @brief STM32 clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h.
+ */
+void stm32_clock_init(void) {
+
+ /* HSI setup.*/
+ RCC->CR = RCC_CR_HSITRIM_RESET_BITS | RCC_CR_HSION;
+ while (!(RCC->CR & RCC_CR_HSIRDY))
+ ; /* Waits until HSI stable. */
+ /* HSE setup.*/
+ RCC->CR |= RCC_CR_HSEON;
+ while (!(RCC->CR & RCC_CR_HSERDY))
+ ; /* Waits until HSE stable. */
+ /* PLL setup.*/
+ RCC->CFGR = RCC_CFGR_PLLSRC_HSE_BITS | PLLPREBITS | PLLMULBITS;
+ RCC->CR |= RCC_CR_PLLON;
+ while (!(RCC->CR & RCC_CR_PLLRDY))
+ ; /* Waits until PLL stable. */
+ /* Clock sources.*/
+ RCC->CFGR |= RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV2 |
+ RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_ADCPRE_DIV8 |
+ RCC_CFGR_MCO_NOCLOCK | USBPREBITS;
+
+ /* Flash setup and final clock selection. */
+ FLASH->ACR = FLASHBITS; /* Flash wait states depending on clock. */
+ RCC->CFGR |= RCC_CFGR_SW_PLL; /* Switches the PLL clock ON. */
+ while ((RCC->CFGR & RCC_CFGR_SW) != RCC_CFGR_SW_PLL)
+ ;
+}
+
+/**
+ * @brief STM32 NVIC/SCB/SYSTICK initialization.
+ * @note All the involved constants come from the file @p board.h.
+ */
+void stm32_nvic_init(void) {
+
+ /* Note: PRIGROUP 4:0 (4:4).*/
+ SCB->AIRCR = AIRCR_VECTKEY | SCB_AIRCR_PRIGROUP_0 | SCB_AIRCR_PRIGROUP_1;
+ NVICSetSystemHandlerPriority(HANDLER_SVCALL, PRIORITY_SVCALL);
+ NVICSetSystemHandlerPriority(HANDLER_SYSTICK, PRIORITY_SYSTICK);
+ NVICSetSystemHandlerPriority(HANDLER_PENDSV, PRIORITY_PENDSV);
+
+ SysTick->LOAD = SYSCLK / (8000000 / CH_FREQUENCY) - 1;
+ SysTick->VAL = 0;
+ SysTick->CTRL = SysTick_CTRL_ENABLE | SysTick_CTRL_TICKINT;
+}
+
+/** @} */
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