Added support for timers 6, 7, 9, 11, 12, 14 to the STM32 GPT driver.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5551 35acf78f-673a-0410-8e92-d51de3d6d3f4

1 files changed, 180 insertions, 3 deletions

diff --git a/os/hal/platforms/STM32/gpt_lld.h b/os/hal/platforms/STM32/gpt_lld.h
index d547bb68b..ecb1dcb35 100644
--- a/os/hal/platforms/STM32/gpt_lld.h
+++ b/os/hal/platforms/STM32/gpt_lld.h
@@ -85,6 +85,24 @@
 #endif

 

 /**

+ * @brief   GPTD6 driver enable switch.

+ * @details If set to @p TRUE the support for GPTD6 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(STM32_GPT_USE_TIM6) || defined(__DOXYGEN__)

+#define STM32_GPT_USE_TIM6                  FALSE

+#endif

+

+/**

+ * @brief   GPTD7 driver enable switch.

+ * @details If set to @p TRUE the support for GPTD7 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(STM32_GPT_USE_TIM7) || defined(__DOXYGEN__)

+#define STM32_GPT_USE_TIM7                  FALSE

+#endif

+

+/**

  * @brief   GPTD8 driver enable switch.

  * @details If set to @p TRUE the support for GPTD8 is included.

  * @note    The default is @p TRUE.

@@ -94,6 +112,42 @@
 #endif

 

 /**

+ * @brief   GPTD9 driver enable switch.

+ * @details If set to @p TRUE the support for GPTD9 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(STM32_GPT_USE_TIM9) || defined(__DOXYGEN__)

+#define STM32_GPT_USE_TIM9                  FALSE

+#endif

+

+/**

+ * @brief   GPTD11 driver enable switch.

+ * @details If set to @p TRUE the support for GPTD11 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(STM32_GPT_USE_TIM11) || defined(__DOXYGEN__)

+#define STM32_GPT_USE_TIM11                 FALSE

+#endif

+

+/**

+ * @brief   GPTD12 driver enable switch.

+ * @details If set to @p TRUE the support for GPTD12 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(STM32_GPT_USE_TIM12) || defined(__DOXYGEN__)

+#define STM32_GPT_USE_TIM12                 FALSE

+#endif

+

+/**

+ * @brief   GPTD14 driver enable switch.

+ * @details If set to @p TRUE the support for GPTD14 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(STM32_GPT_USE_TIM14) || defined(__DOXYGEN__)

+#define STM32_GPT_USE_TIM14                 FALSE

+#endif

+

+/**

  * @brief   GPTD1 interrupt priority level setting.

  */

 #if !defined(STM32_GPT_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)

@@ -129,11 +183,53 @@
 #endif

 

 /**

- * @brief   GPTD5 interrupt priority level setting.

+ * @brief   GPTD6 interrupt priority level setting.

+ */

+#if !defined(STM32_GPT_TIM6_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_GPT_TIM6_IRQ_PRIORITY         7

+#endif

+

+/**

+ * @brief   GPTD7 interrupt priority level setting.

+ */

+#if !defined(STM32_GPT_TIM7_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_GPT_TIM7_IRQ_PRIORITY         7

+#endif

+

+/**

+ * @brief   GPTD8 interrupt priority level setting.

  */

 #if !defined(STM32_GPT_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_GPT_TIM8_IRQ_PRIORITY         7

 #endif

+

+/**

+ * @brief   GPTD9 interrupt priority level setting.

+ */

+#if !defined(STM32_GPT_TIM9_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_GPT_TIM9_IRQ_PRIORITY         7

+#endif

+

+/**

+ * @brief   GPTD11 interrupt priority level setting.

+ */

+#if !defined(STM32_GPT_TIM11_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_GPT_TIM11_IRQ_PRIORITY        7

+#endif

+

+/**

+ * @brief   GPTD12 interrupt priority level setting.

+ */

+#if !defined(STM32_GPT_TIM12_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_GPT_TIM12_IRQ_PRIORITY        7

+#endif

+

+/**

+ * @brief   GPTD14 interrupt priority level setting.

+ */

+#if !defined(STM32_GPT_TIM14_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_GPT_TIM14_IRQ_PRIORITY        7

+#endif

 /** @} */

 

 /*===========================================================================*/

@@ -160,13 +256,40 @@
 #error "TIM5 not present in the selected device"

 #endif

 

+#if STM32_GPT_USE_TIM6 && !STM32_HAS_TIM6

+#error "TIM6 not present in the selected device"

+#endif

+

+#if STM32_GPT_USE_TIM7 && !STM32_HAS_TIM7

+#error "TIM7 not present in the selected device"

+#endif

+

 #if STM32_GPT_USE_TIM8 && !STM32_HAS_TIM8

 #error "TIM8 not present in the selected device"

 #endif

 

+#if STM32_GPT_USE_TIM9 && !STM32_HAS_TIM9

+#error "TIM9 not present in the selected device"

+#endif

+

+#if STM32_GPT_USE_TIM11 && !STM32_HAS_TIM11

+#error "TIM11 not present in the selected device"

+#endif

+

+#if STM32_GPT_USE_TIM12 && !STM32_HAS_TIM12

+#error "TIM12 not present in the selected device"

+#endif

+

+#if STM32_GPT_USE_TIM14 && !STM32_HAS_TIM14

+#error "TIM14 not present in the selected device"

+#endif

+

 #if !STM32_GPT_USE_TIM1 && !STM32_GPT_USE_TIM2 &&                           \

-    !STM32_GPT_USE_TIM3 && !STM32_GPT_USE_TIM4 &&                           \

-    !STM32_GPT_USE_TIM5 && !STM32_GPT_USE_TIM8

+    !STM32_GPT_USE_TIM3 && !STM32_GPT_USE_TIM4 &&  \

+    !STM32_GPT_USE_TIM5 && !STM32_GPT_USE_TIM6 &&  \

+    !STM32_GPT_USE_TIM7 && !STM32_GPT_USE_TIM8 &&  \

+    !STM32_GPT_USE_TIM9 && !STM32_GPT_USE_TIM11 && \

+    !STM32_GPT_USE_TIM12 && !STM32_GPT_USE_TIM14

 #error "GPT driver activated but no TIM peripheral assigned"

 #endif

 

@@ -195,11 +318,41 @@
 #error "Invalid IRQ priority assigned to TIM5"

 #endif

 

+#if STM32_GPT_USE_TIM6 &&                                                   \

+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM6_IRQ_PRIORITY)

+#error "Invalid IRQ priority assigned to TIM6"

+#endif

+

+#if STM32_GPT_USE_TIM7 &&                                                   \

+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM7_IRQ_PRIORITY)

+#error "Invalid IRQ priority assigned to TIM7"

+#endif

+

 #if STM32_GPT_USE_TIM8 &&                                                   \

     !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM8_IRQ_PRIORITY)

 #error "Invalid IRQ priority assigned to TIM8"

 #endif

 

+#if STM32_GPT_USE_TIM9 &&                                                   \

+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM9_IRQ_PRIORITY)

+#error "Invalid IRQ priority assigned to TIM9"

+#endif

+

+#if STM32_GPT_USE_TIM11 &&                                                   \

+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM11_IRQ_PRIORITY)

+#error "Invalid IRQ priority assigned to TIM11"

+#endif

+

+#if STM32_GPT_USE_TIM12 &&                                                   \

+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM12_IRQ_PRIORITY)

+#error "Invalid IRQ priority assigned to TIM12"

+#endif

+

+#if STM32_GPT_USE_TIM14 &&                                                   \

+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_GPT_TIM14_IRQ_PRIORITY)

+#error "Invalid IRQ priority assigned to TIM14"

+#endif

+

 /*===========================================================================*/

 /* Driver data structures and types.                                         */

 /*===========================================================================*/

@@ -303,10 +456,34 @@ extern GPTDriver GPTD4;
 extern GPTDriver GPTD5;

 #endif

 

+#if STM32_GPT_USE_TIM6 && !defined(__DOXYGEN__)

+extern GPTDriver GPTD6;

+#endif

+

+#if STM32_GPT_USE_TIM7 && !defined(__DOXYGEN__)

+extern GPTDriver GPTD7;

+#endif

+

 #if STM32_GPT_USE_TIM8 && !defined(__DOXYGEN__)

 extern GPTDriver GPTD8;

 #endif

 

+#if STM32_GPT_USE_TIM9 && !defined(__DOXYGEN__)

+extern GPTDriver GPTD9;

+#endif

+

+#if STM32_GPT_USE_TIM11 && !defined(__DOXYGEN__)

+extern GPTDriver GPTD11;

+#endif

+

+#if STM32_GPT_USE_TIM12 && !defined(__DOXYGEN__)

+extern GPTDriver GPTD12;

+#endif

+

+#if STM32_GPT_USE_TIM14 && !defined(__DOXYGEN__)

+extern GPTDriver GPTD14;

+#endif

+

 #ifdef __cplusplus

 extern "C" {

 #endif