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authorbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2011-12-16 14:42:23 +0000
committerbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2011-12-16 14:42:23 +0000
commit968d0cf6e9e8f362021e4288cd3336fe7922e00e (patch)
treebe576765d1d02f9ad6b36f18542f0f4f06295740 /os/hal/platforms/STM32/RTCv1
parent172680aea3057dcea62fc4a053510d2dd03bb911 (diff)
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RTC. High level API rolled back.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3619 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32/RTCv1')
-rw-r--r--os/hal/platforms/STM32/RTCv1/rtc_lld.c28
1 files changed, 15 insertions, 13 deletions
diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.c b/os/hal/platforms/STM32/RTCv1/rtc_lld.c
index 2e95bc446..1097e1e9b 100644
--- a/os/hal/platforms/STM32/RTCv1/rtc_lld.c
+++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.c
@@ -60,16 +60,16 @@ static void rtc_lld_serve_interrupt(RTCDriver *rtcp) {
chSysLockFromIsr();
if ((RTC->CRH & RTC_CRH_SECIE) && (RTC->CRL & RTC_CRL_SECF)) {
- RTC->CRL &= ~RTC_CRL_SECF;
rtcp->rtc_cb(rtcp, RTC_EVENT_SECOND);
+ RTC->CRL &= ~RTC_CRL_SECF;
}
if ((RTC->CRH & RTC_CRH_ALRIE) && (RTC->CRL & RTC_CRL_ALRF)) {
- RTC->CRL &= ~RTC_CRL_ALRF;
- rtcp->rtc_cb(rtcp, RTC_EVENT_ALARM);
+ rtcp->rtc_cb(rtcp, RTC_EVENT_ALARM);
+ RTC->CRL &= ~RTC_CRL_ALRF;
}
if ((RTC->CRH & RTC_CRH_OWIE) && (RTC->CRL & RTC_CRL_OWF)) {
- RTC->CRL &= ~RTC_CRL_OWF;
rtcp->rtc_cb(rtcp, RTC_EVENT_OVERFLOW);
+ RTC->CRL &= ~RTC_CRL_OWF;
}
chSysUnlockFromIsr();
@@ -138,6 +138,7 @@ void rtc_lld_init(void){
while (!(RCC->BDCR & RCC_BDCR_LSERDY))
;
}
+ preload = STM32_LSECLK - 1;
#elif STM32_RTC == STM32_RTC_LSI
#define RTC_CLK STM32_LSICLK
/* TODO: Move the LSI clock initialization in the HAL low level driver.*/
@@ -150,12 +151,12 @@ void rtc_lld_init(void){
volatile uint32_t tmo = (STM32_SYSCLK / 1000000) * 100;
while (tmo--)
;
+ preload = STM32_LSICLK - 1;
#elif STM32_RTC == STM32_RTC_HSE
#define RTC_CLK (STM32_HSECLK / 128)
+ preload = (STM32_HSECLK / 128) - 1;
#endif
- preload = RTC_CLK - 1;
-
/* Selects clock source (previously enabled and stabilized).*/
RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTC;
@@ -278,8 +279,8 @@ void rtc_lld_set_alarm(RTCDriver *rtcp,
*
* @note Default value after BKP domain reset is 0xFFFFFFFF.
*
- * @param[in] rtcp pointer to RTC driver structure
- * @param[in] alarm alarm identifier
+ * @param[in] rtcp pointer to RTC driver structure
+ * @param[in] alarm alarm identifier
* @param[out] alarmspec pointer to a @p RTCAlarm structure
*
* @notapi
@@ -304,13 +305,14 @@ void rtc_lld_get_alarm(RTCDriver *rtcp,
*
* @notapi
*/
-void rtc_lld_set_callback(RTCDriver *rtcp, RTCCallbackConfig *cb_cfg) {
+void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) {
+
+ if (callback != NULL) {
+ rtcp->rtc_cb = callback;
- if (cb_cfg->rtc_cb != NULL) {
- rtcp->rtc_cb = cb_cfg->rtc_cb;
/* Interrupts are enabled only after setting up the callback, this
- way there is no need to check for the NULL callback pointer inside
- the IRQ handler.*/
+ way there is no need to check for the NULL callback pointer inside
+ the IRQ handler.*/
rtc_lld_wait_write();
RTC->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF);
rtc_lld_wait_write();