git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5372 35acf78f-673a-0410-8e92-d51de3d6d3f4

4 files changed, 210 insertions, 186 deletions

diff --git a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c
index 908d634b0..864a43540 100644
--- a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c
+++ b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c
@@ -13,8 +13,8 @@
  */

 

 /**

- * @file    SPC560Pxx/pwm_lld.c

- * @brief   SPC560Pxx low level FlexPWM driver code.

+ * @file    FlexPWM_v1/pwm_lld.c

+ * @brief   SPC5xx low level PWM driver code.

  *

  * @addtogroup PWM

  * @{

@@ -78,7 +78,6 @@ PWMDriver PWMD4;
  * @notapi

  */

 void pwm_lld_start_submodule(PWMDriver *pwmp, uint8_t sid) {

-

   pwmcnt_t pwmperiod;

   uint32_t psc;

 

@@ -91,36 +90,38 @@ void pwm_lld_start_submodule(PWMDriver *pwmp, uint8_t sid) {
   pwmp->flexpwmp->SUB[sid].INTEN.R = 0x0000;

 

   /* Setting PWM clock frequency and submodule prescaler.*/

-  psc = (SPC5_FLEXPWM0_CLK / pwmp->config->frequency);

+  psc = SPC5_FLEXPWM0_CLK / pwmp->config->frequency;

+

   chDbgAssert((psc <= 0xFFFF) &&

-      (((psc) * pwmp->config->frequency) == SPC5_FLEXPWM0_CLK) &&

-      ((psc == 1) || (psc == 2) || (psc == 4) || (psc == 8) ||

-          (psc == 16) || (psc == 32) ||

-          (psc == 64) || (psc == 128)),

-      "icu_lld_start(), #1", "invalid frequency");

-  switch(psc) {

-    case 1:

+              (((psc) * pwmp->config->frequency) == SPC5_FLEXPWM0_CLK) &&

+              ((psc == 1) || (psc == 2) || (psc == 4) || (psc == 8) ||

+               (psc == 16) || (psc == 32) ||

+               (psc == 64) || (psc == 128)),

+              "icu_lld_start(), #1", "invalid frequency");

+

+  switch (psc) {

+  case 1:

     pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = 0b000;

     break;

-    case 2:

+  case 2:

     pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = 0b001;

     break;

-    case 4:

+  case 4:

     pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = 0b010;

     break;

-    case 8:

+  case 8:

     pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = 0b011;

     break;

-    case 16:

+  case 16:

     pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = 0b100;

     break;

-    case 32:

+  case 32:

     pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = 0b101;

     break;

-    case 64:

+  case 64:

     pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = 0b110;

     break;

-    case 128:

+  case 128:

     pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = 0b111;

     break;

   }

@@ -138,7 +139,7 @@ void pwm_lld_start_submodule(PWMDriver *pwmp, uint8_t sid) {
 

   /* Sets the submodule channels.*/

   switch (pwmp->config->mode & PWM_OUTPUT_MASK) {

-    case EDGE_ALIGNED_PWM:

+  case EDGE_ALIGNED_PWM:

     /* Setting reloads.*/

     pwmp->flexpwmp->SUB[sid].CTRL.B.HALF = 0;

     pwmp->flexpwmp->SUB[sid].CTRL.B.FULL = 1;

@@ -147,117 +148,117 @@ void pwm_lld_start_submodule(PWMDriver *pwmp, uint8_t sid) {
     pwmp->flexpwmp->SUB[sid].VAL[2].R = ~(pwmperiod / 2) + 1U;

     pwmp->flexpwmp->SUB[sid].VAL[4].R = ~(pwmperiod / 2) + 1U;

     break;

-    case CENTER_ALIGNED_PWM:

+  case CENTER_ALIGNED_PWM:

     /* Setting reloads.*/

     pwmp->flexpwmp->SUB[sid].CTRL.B.HALF = 1;

     pwmp->flexpwmp->SUB[sid].CTRL.B.FULL = 0;

     break;

-    default:

+  default:

     ;

   }

 

   /* Polarities setup.*/

   switch (pwmp->config->channels[0].mode & PWM_OUTPUT_MASK) {

-    case PWM_OUTPUT_ACTIVE_LOW:

+  case PWM_OUTPUT_ACTIVE_LOW:

     pwmp->flexpwmp->SUB[sid].OCTRL.B.POLA = 1;

     /* Enables CHA mask.*/

     pwmp->flexpwmp->MASK.B.MASKA |= (0b0000 | (1U << sid));

     /* Enables CHA.*/

     pwmp->flexpwmp->OUTEN.B.PWMA_EN |= (0b0000 | (1U << sid));

     break;

-    case PWM_OUTPUT_ACTIVE_HIGH:

+  case PWM_OUTPUT_ACTIVE_HIGH:

     pwmp->flexpwmp->SUB[sid].OCTRL.B.POLA = 0;

     /* Enables CHA mask.*/

     pwmp->flexpwmp->MASK.B.MASKA |= (0b0000 | (1U << sid));

     /* Enables CHA.*/

     pwmp->flexpwmp->OUTEN.B.PWMA_EN |= (0b0000 | (1U << sid));

     break;

-    case PWM_OUTPUT_DISABLED:

+  case PWM_OUTPUT_DISABLED:

     /* Enables CHA mask.*/

     pwmp->flexpwmp->MASK.B.MASKA |= (0b0000 | (1U << sid));

     break;

-    default:

+  default:

     ;

   }

   switch (pwmp->config->channels[1].mode & PWM_OUTPUT_MASK) {

-    case PWM_OUTPUT_ACTIVE_LOW:

+  case PWM_OUTPUT_ACTIVE_LOW:

     pwmp->flexpwmp->SUB[sid].OCTRL.B.POLB = 1;

     /* Enables CHB mask.*/

     pwmp->flexpwmp->MASK.B.MASKB |= (0b0000 | (1U << sid));

     /* Enables CHB.*/

     pwmp->flexpwmp->OUTEN.B.PWMB_EN |= (0b0000 | (1U << sid));

     break;

-    case PWM_OUTPUT_ACTIVE_HIGH:

+  case PWM_OUTPUT_ACTIVE_HIGH:

     pwmp->flexpwmp->SUB[sid].OCTRL.B.POLB = 0;

     /* Enables CHB mask.*/

     pwmp->flexpwmp->MASK.B.MASKB |= (0b0000 | (1U << sid));

     /* Enables CHB.*/

     pwmp->flexpwmp->OUTEN.B.PWMB_EN |= (0b0000 | (1U << sid));

     break;

-    case PWM_OUTPUT_DISABLED:

+  case PWM_OUTPUT_DISABLED:

     /* Enables CHB mask.*/

     pwmp->flexpwmp->MASK.B.MASKB |= (0b0000 | (1U << sid));

     break;

-    default:

+  default:

     ;

   }

 

   /* Complementary output setup.*/

-  /*  switch (pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {

-   case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:

-   chDbgAssert(pwmp->config->channels[1].mode == PWM_OUTPUT_ACTIVE_LOW,

-   "pwm_lld_start(), #1",

-   "the PWM chB must be set in PWM_OUTPUT_ACTIVE_LOW");

-   //pwmp->flexpwmp->SUB[sid].OCTRL.B.POLA = 1;

-   pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;

-   pwmp->flexpwmp->MCTRL.B.IPOL |= (0b0000 | (1U << sid));

-   pwmp->flexpwmp->MASK.B.MASKA |= (0b0000 | (1U << sid));

-   pwmp->flexpwmp->OUTEN.B.PWMA_EN |= (0b0000 | (1U << sid));

-   //pwmp->flexpwmp->SUB[0].OCTRL.B.POLB = 0;

-   break;

-   case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:

-   chDbgAssert(pwmp->config->channels[1].mode == PWM_OUTPUT_ACTIVE_HIGH,

-   "pwm_lld_start(), #2",

-   "the PWM chB must be set in PWM_OUTPUT_ACTIVE_HIGH");

-   pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;

-   pwmp->flexpwmp->MCTRL.B.IPOL |= (0b0000 | (0U << sid));

-   pwmp->flexpwmp->MASK.B.MASKA |= (0b0000 | (1U << sid));

-   pwmp->flexpwmp->OUTEN.B.PWMA_EN |= (0b0000 | (1U << sid));

-   // pwmp->flexpwmp->SUB[0].OCTRL.B.POLA = 0;

-   //pwmp->flexpwmp->SUB[0].OCTRL.B.POLB = 1;

-   break;

-   default:

-   ;

-   }

-

-   switch (pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {

-   case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:

-   chDbgAssert(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW,

-   "pwm_lld_start(), #3",

-   "the PWM chA must be set in PWM_OUTPUT_ACTIVE_LOW");

-   pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;

-   pwmp->flexpwmp->MCTRL.B.IPOL &= ~ (0b0000 | (1U << sid));

-   //  pwmp->flexpwmp->SUB[0].OCTRL.B.POLA = 0;

-   pwmp->flexpwmp->SUB[sid].OCTRL.B.POLB = 1;

-   pwmp->flexpwmp->MASK.B.MASKB |= (0b0000 | (1U << sid));

-   pwmp->flexpwmp->OUTEN.B.PWMB_EN |= (0b0000 | (1U << sid));

-   break;

-   case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:

-   chDbgAssert(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_HIGH,

-   "pwm_lld_start(), #4",

-   "the PWM chA must be set in PWM_OUTPUT_ACTIVE_HIGH");

-   pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;

-   pwmp->flexpwmp->MCTRL.B.IPOL &= ~ (0b0000 | (1U << sid));

-

-   pwmp->flexpwmp->MASK.B.MASKB |= (0b0000 | (1U << sid));

-   pwmp->flexpwmp->OUTEN.B.PWMB_EN |= (0b0000 | (1U << sid));

-   // pwmp->flexpwmp->SUB[0].OCTRL.B.POLA = 1;

-   // pwmp->flexpwmp->SUB[0].OCTRL.B.POLB = 0;

-   break;

-   default:

-   ;

-   }

-   */

+/*  switch (pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {

+  case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:

+    chDbgAssert(pwmp->config->channels[1].mode == PWM_OUTPUT_ACTIVE_LOW,

+                "pwm_lld_start(), #1",

+                "the PWM chB must be set in PWM_OUTPUT_ACTIVE_LOW");

+    //pwmp->flexpwmp->SUB[sid].OCTRL.B.POLA = 1;

+    pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;

+    pwmp->flexpwmp->MCTRL.B.IPOL |= (0b0000 | (1U << sid));

+    pwmp->flexpwmp->MASK.B.MASKA |= (0b0000 | (1U << sid));

+    pwmp->flexpwmp->OUTEN.B.PWMA_EN |= (0b0000 | (1U << sid));

+    //pwmp->flexpwmp->SUB[0].OCTRL.B.POLB = 0;

+    break;

+  case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:

+    chDbgAssert(pwmp->config->channels[1].mode == PWM_OUTPUT_ACTIVE_HIGH,

+                "pwm_lld_start(), #2",

+                "the PWM chB must be set in PWM_OUTPUT_ACTIVE_HIGH");

+    pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;

+    pwmp->flexpwmp->MCTRL.B.IPOL |= (0b0000 | (0U << sid));

+    pwmp->flexpwmp->MASK.B.MASKA |= (0b0000 | (1U << sid));

+    pwmp->flexpwmp->OUTEN.B.PWMA_EN |= (0b0000 | (1U << sid));

+    // pwmp->flexpwmp->SUB[0].OCTRL.B.POLA = 0;

+    //pwmp->flexpwmp->SUB[0].OCTRL.B.POLB = 1;

+    break;

+  default:

+    ;

+  }

+

+  switch (pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {

+  case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:

+    chDbgAssert(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW,

+                "pwm_lld_start(), #3",

+                "the PWM chA must be set in PWM_OUTPUT_ACTIVE_LOW");

+    pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;

+    pwmp->flexpwmp->MCTRL.B.IPOL &= ~ (0b0000 | (1U << sid));

+    //  pwmp->flexpwmp->SUB[0].OCTRL.B.POLA = 0;

+    pwmp->flexpwmp->SUB[sid].OCTRL.B.POLB = 1;

+    pwmp->flexpwmp->MASK.B.MASKB |= (0b0000 | (1U << sid));

+    pwmp->flexpwmp->OUTEN.B.PWMB_EN |= (0b0000 | (1U << sid));

+    break;

+  case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:

+    chDbgAssert(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_HIGH,

+                "pwm_lld_start(), #4",

+                "the PWM chA must be set in PWM_OUTPUT_ACTIVE_HIGH");

+    pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;

+    pwmp->flexpwmp->MCTRL.B.IPOL &= ~ (0b0000 | (1U << sid));

+

+    pwmp->flexpwmp->MASK.B.MASKB |= (0b0000 | (1U << sid));

+    pwmp->flexpwmp->OUTEN.B.PWMB_EN |= (0b0000 | (1U << sid));

+    // pwmp->flexpwmp->SUB[0].OCTRL.B.POLA = 1;

+    // pwmp->flexpwmp->SUB[0].OCTRL.B.POLB = 0;

+    break;

+  default:

+    ;

+  }

+*/

 

   /* Sets the INIT and MASK registers.*/

   pwmp->flexpwmp->SUB[sid].CTRL2.B.FRCEN = 1U;

@@ -280,9 +281,8 @@ void pwm_lld_start_submodule(PWMDriver *pwmp, uint8_t sid) {
  * @notapi

  */

 void pwm_lld_enable_submodule_channel(PWMDriver *pwmp,

-    pwmchannel_t channel,

-    pwmcnt_t width, uint8_t sid) {

-

+                                  pwmchannel_t channel,

+                                  pwmcnt_t width, uint8_t sid) {

   pwmcnt_t pwmperiod;

   int16_t nwidth;

   pwmperiod = pwmp->period;

@@ -301,23 +301,23 @@ void pwm_lld_enable_submodule_channel(PWMDriver *pwmp,
 

     /* Sets the channel width.*/

     switch (pwmp->config->mode & PWM_OUTPUT_MASK) {

-      case EDGE_ALIGNED_PWM:

-      if(nwidth >= 0)

-      pwmp->flexpwmp->SUB[sid].VAL[3].R = nwidth;

+    case EDGE_ALIGNED_PWM:

+      if (nwidth >= 0)

+        pwmp->flexpwmp->SUB[sid].VAL[3].R = nwidth;

       else

-      pwmp->flexpwmp->SUB[sid].VAL[3].R = ~((pwmperiod / 2) - width) + 1U;

+        pwmp->flexpwmp->SUB[sid].VAL[3].R = ~((pwmperiod / 2) - width) + 1U;

       break;

-      case CENTER_ALIGNED_PWM:

+    case CENTER_ALIGNED_PWM:

       pwmp->flexpwmp->SUB[sid].VAL[3].R = width / 2;

       pwmp->flexpwmp->SUB[sid].VAL[2].R = ~(width / 2) + 1U;

       break;

-      default:

+    default:

       ;

     }

 

     /* Removes the channel mask if it is necessary.*/

     if ((pwmp->flexpwmp->MASK.B.MASKA & (0b0000 | (1U << sid))) == 1)

-    pwmp->flexpwmp->MASK.B.MASKA &= ~ (0b0000 | (1U << sid));

+      pwmp->flexpwmp->MASK.B.MASKA &= ~ (0b0000 | (1U << sid));

   }

   /* Active the width interrupt.*/

   else if (channel == 1) {

@@ -328,23 +328,23 @@ void pwm_lld_enable_submodule_channel(PWMDriver *pwmp,
     }

     /* Sets the channel width.*/

     switch (pwmp->config->mode & PWM_OUTPUT_MASK) {

-      case EDGE_ALIGNED_PWM:

-      if(nwidth >= 0)

-      pwmp->flexpwmp->SUB[sid].VAL[5].R = nwidth;

+    case EDGE_ALIGNED_PWM:

+      if (nwidth >= 0)

+        pwmp->flexpwmp->SUB[sid].VAL[5].R = nwidth;

       else

-      pwmp->flexpwmp->SUB[sid].VAL[5].R = ~((pwmperiod / 2) - width) + 1U;

+        pwmp->flexpwmp->SUB[sid].VAL[5].R = ~((pwmperiod / 2) - width) + 1U;

       break;

-      case CENTER_ALIGNED_PWM:

+    case CENTER_ALIGNED_PWM:

       pwmp->flexpwmp->SUB[sid].VAL[5].R = width / 2;

       pwmp->flexpwmp->SUB[sid].VAL[4].R = ~(width / 2) + 1U;

       break;

-      default:

+    default:

       ;

     }

 

     /* Removes the channel mask if it is necessary.*/

     if ((pwmp->flexpwmp->MASK.B.MASKB & (0b0000 | (1U << sid))) == 1)

-    pwmp->flexpwmp->MASK.B.MASKB &= ~ (0b0000 | (1U << sid));

+      pwmp->flexpwmp->MASK.B.MASKB &= ~ (0b0000 | (1U << sid));

   }

 

   /* Active the periodic interrupt.*/

@@ -373,8 +373,8 @@ void pwm_lld_enable_submodule_channel(PWMDriver *pwmp,
  * @notapi

  */

 void pwm_lld_disable_submodule_channel(PWMDriver *pwmp,

-    pwmchannel_t channel,

-    uint8_t sid) {

+                                   pwmchannel_t channel,

+                                   uint8_t sid) {

 

   pwmp->flexpwmp->MCTRL.B.CLDOK |= (0b0000 | (1U << sid));

 

@@ -407,12 +407,12 @@ void pwm_lld_disable_submodule_channel(PWMDriver *pwmp,
   pwmp->flexpwmp->SUB[sid].CTRL2.B.FORCE = 1U;

 

   /* Disable RIE interrupt to prevent reload interrupt.*/

-  if((pwmp->flexpwmp->MASK.B.MASKA & (0b0000 | (1U << sid))) &&

+  if ((pwmp->flexpwmp->MASK.B.MASKA & (0b0000 | (1U << sid))) &&

       (pwmp->flexpwmp->MASK.B.MASKB & (0b0000 | (1U << sid))) == 1) {

     pwmp->flexpwmp->SUB[sid].INTEN.B.RIE = 0;

     /* Clear the reload flag.*/

     pwmp->flexpwmp->SUB[sid].STS.B.RF = 1U;

-  }

+    }

 

   pwmp->flexpwmp->MCTRL.B.LDOK |= (0b0000 | (1U << sid));

 }

@@ -428,8 +428,8 @@ void pwm_lld_disable_submodule_channel(PWMDriver *pwmp,
  * @param[in] pwmp      pointer to a @p PWMDriver object

  */

 static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {

-

   uint16_t sr;

+

 #if SPC5_PWM_USE_SMOD0

   if (&PWMD1 == pwmp) {

     sr = pwmp->flexpwmp->SUB[0].STS.R & pwmp->flexpwmp->SUB[0].INTEN.R;

@@ -724,23 +724,23 @@ void pwm_lld_start(PWMDriver *pwmp) {
 

 #if SPC5_PWM_USE_SMOD0

     if (PWMD1.state == PWM_READY)

-    SMOD0 = 1U;

+      SMOD0 = 1U;

 #endif

 #if SPC5_PWM_USE_SMOD1

     if (PWMD2.state == PWM_READY)

-    SMOD1 = 1U;

+      SMOD1 = 1U;

 #endif

 #if SPC5_PWM_USE_SMOD2

     if (PWMD3.state == PWM_READY)

-    SMOD2 = 1U;

+      SMOD2 = 1U;

 #endif

 #if SPC5_PWM_USE_SMOD3

     if (PWMD4.state == PWM_READY)

-    SMOD3 = 1U;

+      SMOD3 = 1U;

 #endif

 

     /* Set Peripheral Clock.*/

-    if(!(SMOD0 || SMOD1 || SMOD2 || SMOD3)) {

+    if (!(SMOD0 || SMOD1 || SMOD2 || SMOD3)) {

       halSPCSetPeripheralClockMode(SPC5_FLEXPWM0_PCTL,

           SPC5_PWM_FLEXPWM0_START_PCTL);

     }

@@ -913,7 +913,7 @@ void pwm_lld_stop(PWMDriver *pwmp) {
         (pwmp->flexpwmp->MCTRL.B.RUN & 0b0100) ||

         (pwmp->flexpwmp->MCTRL.B.RUN & 0b1000) == 0) {

       halSPCSetPeripheralClockMode(SPC5_FLEXPWM0_PCTL,

-          SPC5_PWM_FLEXPWM0_STOP_PCTL);

+                                   SPC5_PWM_FLEXPWM0_STOP_PCTL);

     }

   }

 }

@@ -931,8 +931,8 @@ void pwm_lld_stop(PWMDriver *pwmp) {
  * @notapi

  */

 void pwm_lld_enable_channel(PWMDriver *pwmp,

-    pwmchannel_t channel,

-    pwmcnt_t width) {

+                            pwmchannel_t channel,

+                            pwmcnt_t width) {

 

 #if SPC5_PWM_USE_SMOD0

   if (&PWMD1 == pwmp) {

@@ -1010,7 +1010,6 @@ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
  */

 void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {

 

-  (void)period;

   pwmcnt_t pwmperiod;

   pwmperiod = period;

 #if SPC5_PWM_USE_SMOD0

@@ -1023,13 +1022,13 @@ void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
     pwmp->flexpwmp->SUB[0].VAL[1].R = pwmperiod / 2;

 

     switch (pwmp->config->mode & PWM_OUTPUT_MASK) {

-      case EDGE_ALIGNED_PWM:

+    case EDGE_ALIGNED_PWM:

 

       /* Setting active front of PWM channels.*/

       pwmp->flexpwmp->SUB[0].VAL[2].R = ~(pwmperiod / 2) + 1U;

       pwmp->flexpwmp->SUB[0].VAL[4].R = ~(pwmperiod / 2) + 1U;

       break;

-      default:

+    default:

       ;

     }

     pwmp->flexpwmp->MCTRL.B.LDOK |= 0b0001;

@@ -1045,13 +1044,13 @@ void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
     pwmp->flexpwmp->SUB[1].VAL[1].R = pwmperiod / 2;

 

     switch (pwmp->config->mode & PWM_OUTPUT_MASK) {

-      case EDGE_ALIGNED_PWM:

+    case EDGE_ALIGNED_PWM:

 

       /* Setting active front of PWM channels.*/

       pwmp->flexpwmp->SUB[1].VAL[2].R = ~(pwmperiod / 2) + 1U;

       pwmp->flexpwmp->SUB[1].VAL[4].R = ~(pwmperiod / 2) + 1U;

       break;

-      default:

+    default:

       ;

     }

     pwmp->flexpwmp->MCTRL.B.LDOK |= 0b0010;

@@ -1067,13 +1066,13 @@ void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
     pwmp->flexpwmp->SUB[2].VAL[1].R = pwmperiod / 2;

 

     switch (pwmp->config->mode & PWM_OUTPUT_MASK) {

-      case EDGE_ALIGNED_PWM:

+    case EDGE_ALIGNED_PWM:

 

       /* Setting active front of PWM channels.*/

       pwmp->flexpwmp->SUB[2].VAL[2].R = ~(pwmperiod / 2) + 1U;

       pwmp->flexpwmp->SUB[2].VAL[4].R = ~(pwmperiod / 2) + 1U;

       break;

-      default:

+    default:

       ;

     }

     pwmp->flexpwmp->MCTRL.B.LDOK |= 0b0100;

@@ -1089,13 +1088,12 @@ void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
     pwmp->flexpwmp->SUB[3].VAL[1].R = pwmperiod / 2;

 

     switch (pwmp->config->mode & PWM_OUTPUT_MASK) {

-      case EDGE_ALIGNED_PWM:

-

+    case EDGE_ALIGNED_PWM:

       /* Setting active front of PWM channels.*/

       pwmp->flexpwmp->SUB[3].VAL[2].R = ~(pwmperiod / 2) + 1U;

       pwmp->flexpwmp->SUB[3].VAL[4].R = ~(pwmperiod / 2) + 1U;

       break;

-      default:

+    default:

       ;

     }

     pwmp->flexpwmp->MCTRL.B.LDOK |= 0b1000;

diff --git a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h
index e7b9cf6af..cc1ee0dc1 100644
--- a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h
+++ b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h
@@ -13,8 +13,8 @@
  */

 

 /**

- * @file    SPC560Pxx/pwm_lld.h

- * @brief   SPC560Pxx low level FlexPWM driver header.

+ * @file    FlexPWM_v1/pwm_lld.h

+ * @brief   SPC5xx low level PWM driver header.

  *

  * @addtogroup PWM

  * @{

@@ -33,17 +33,17 @@
  * @name    LINIER register bits definitions

  * @{

  */

-#define SPC5_STS_CMPF0                      (1U << 0)

-#define SPC5_STS_CMPF1                      (1U << 1)

-#define SPC5_STS_CMPF2                      (1U << 2)

-#define SPC5_STS_CMPF3                      (1U << 3)

-#define SPC5_STS_CMPF4                      (1U << 4)

-#define SPC5_STS_CMPF5                      (1U << 5)

-#define SPC5_STS_CFX0                       (1U << 6)

-#define SPC5_STS_CFX1                       (1U << 7)

-#define SPC5_STS_RF                         (1U << 12)

-#define SPC5_STS_REF                        (1U << 13)

-#define SPC5_STS_RUF                        (1U << 14)

+#define SPC5_STS_CMPF0                          (1U << 0)

+#define SPC5_STS_CMPF1                          (1U << 1)

+#define SPC5_STS_CMPF2                          (1U << 2)

+#define SPC5_STS_CMPF3                          (1U << 3)

+#define SPC5_STS_CMPF4                          (1U << 4)

+#define SPC5_STS_CMPF5                          (1U << 5)

+#define SPC5_STS_CFX0                           (1U << 6)

+#define SPC5_STS_CFX1                           (1U << 7)

+#define SPC5_STS_RF                             (1U << 12)

+#define SPC5_STS_REF                            (1U << 13)

+#define SPC5_STS_RUF                            (1U << 14)

 /** @} */

 

 /**

@@ -79,13 +79,13 @@
  * @brief   Edge-Aligned PWM functional mode.

  * @note    This is an SPC5-specific setting.

  */

-#define EDGE_ALIGNED_PWM     0x01

+#define EDGE_ALIGNED_PWM                        0x01

 

 /**

  * @brief   Center-Aligned PWM functional mode.

  * @note    This is an SPC5-specific setting.

  */

-#define CENTER_ALIGNED_PWM     0x02

+#define CENTER_ALIGNED_PWM                      0x02

 

 /*===========================================================================*/

 /* Driver pre-compile time settings.                                         */

@@ -136,28 +136,28 @@
  * @brief   PWMD1 interrupt priority level setting.

  */

 #if !defined(SPC5_PWM_SMOD0_PRIORITY) || defined(__DOXYGEN__)

-#define SPC5_PWM_SMOD0_PRIORITY          7

+#define SPC5_PWM_SMOD0_PRIORITY             7

 #endif

 

 /**

  * @brief   PWMD2 interrupt priority level setting.

  */

 #if !defined(SPC5_PWM_SMOD1_PRIORITY) || defined(__DOXYGEN__)

-#define SPC5_PWM_SMOD1_PRIORITY          7

+#define SPC5_PWM_SMOD1_PRIORITY             7

 #endif

 

 /**

  * @brief   PWMD3 interrupt priority level setting.

  */

 #if !defined(SPC5_PWM_SMOD2_PRIORITY) || defined(__DOXYGEN__)

-#define SPC5_PWM_SMOD2_PRIORITY          7

+#define SPC5_PWM_SMOD2_PRIORITY             7

 #endif

 

 /**

  * @brief   PWMD4 interrupt priority level setting.

  */

 #if !defined(SPC5_PWM_SMOD3_PRIORITY) || defined(__DOXYGEN__)

-#define SPC5_PWM_SMOD3_PRIORITY          7

+#define SPC5_PWM_SMOD3_PRIORITY             7

 #endif

 

 /**

@@ -167,8 +167,8 @@
  *          are defined in @p hal_lld.h.

  */

 #if !defined(SPC5_PWM_FLEXPWM0_START_PCTL) || defined(__DOXYGEN__)

-#define SPC5_PWM_FLEXPWM0_START_PCTL     (SPC5_ME_PCTL_RUN(1) |               \

-                                          SPC5_ME_PCTL_LP(2))

+#define SPC5_PWM_FLEXPWM0_START_PCTL        (SPC5_ME_PCTL_RUN(1) |          \

+                                             SPC5_ME_PCTL_LP(2))

 #endif

 

 /**

@@ -178,8 +178,8 @@
  *          are defined in @p hal_lld.h.

  */

 #if !defined(SPC5_PWM_FLEXPWM0_STOP_PCTL) || defined(__DOXYGEN__)

-#define SPC5_PWM_FLEXPWM0_STOP_PCTL      (SPC5_ME_PCTL_RUN(0) |               \

-                                          SPC5_ME_PCTL_LP(0))

+#define SPC5_PWM_FLEXPWM0_STOP_PCTL         (SPC5_ME_PCTL_RUN(0) |          \

+                                             SPC5_ME_PCTL_LP(0))

 #endif

 

 /*===========================================================================*/

diff --git a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c b/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c
index 68ca17b0b..19445b1c6 100644
--- a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c
+++ b/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c
@@ -13,8 +13,8 @@
  */

 

 /**

- * @file

- * @brief   SPC5xx low level icu driver header.

+ * @file    eTimer_v1/icu_lld.c

+ * @brief   SPC5xx low level ICU driver header.

  *

  * @addtogroup ICU

  * @{

@@ -144,11 +144,14 @@ ICUDriver ICUD12;
  * @param[in] index      ICU channel index

  */

 static void spc5_icu_channel_enable(ICUDriver *icup, uint8_t index) {

+

   /* Clear pending IRQs (if any).*/

   icup->etimerp->CHANNEL[index].STS.R = 0xFFFF;

+

   /* Set Capture 1 and Capture 2 Mode.*/

   icup->etimerp->CHANNEL[index].CCCTRL.B.CPT1MODE = 0b10;

   icup->etimerp->CHANNEL[index].CCCTRL.B.CPT2MODE = 0b01;

+

   /* Active interrupts.*/

   if (icup->config->period_cb != NULL || icup->config->width_cb != NULL) {

     icup->etimerp->CHANNEL[index].INTDMA.B.ICF1IE = 1U;

@@ -157,8 +160,10 @@ static void spc5_icu_channel_enable(ICUDriver *icup, uint8_t index) {
   if (icup->config->overflow_cb != NULL) {

     icup->etimerp->CHANNEL[index].INTDMA.B.TOFIE = 1U;

   }

+

   /* Set Capture FIFO Water Mark.*/

   icup->etimerp->CHANNEL[index].CCCTRL.B.CFWM = 0b00;

+

   /* Enable Counter.*/

   if (ICU_SKIP_FIRST_CAPTURE) {

     icup->etimerp->CHANNEL[index].CTRL.B.CNTMODE = 0b011;

@@ -166,6 +171,7 @@ static void spc5_icu_channel_enable(ICUDriver *icup, uint8_t index) {
   else {

     icup->etimerp->CHANNEL[index].CTRL.B.CNTMODE = 0b001;

   }

+

   /* Enable Capture process.*/

   icup->etimerp->CHANNEL[index].CCCTRL.B.ARM = 1U;

 }

@@ -177,13 +183,17 @@ static void spc5_icu_channel_enable(ICUDriver *icup, uint8_t index) {
  * @param[in] index      ICU channel index

  */

 static void spc5_icu_channel_disable(ICUDriver *icup, uint8_t index) {

+

   /* Disable Capture process.*/

   icup->etimerp->CHANNEL[index].CCCTRL.B.ARM = 0;

+

   /* Clear pending IRQs (if any).*/

   icup->etimerp->CHANNEL[index].STS.R = 0xFFFF;

+

   /* Set Capture 1 and Capture 2 Mode to Disabled.*/

   icup->etimerp->CHANNEL[index].CCCTRL.B.CPT1MODE = 0b00;

   icup->etimerp->CHANNEL[index].CCCTRL.B.CPT2MODE = 0b00;

+

   /* Disable interrupts.*/

   if (icup->config->period_cb != NULL || icup->config->width_cb != NULL) {

     icup->etimerp->CHANNEL[index].INTDMA.B.ICF1IE = 0;

@@ -200,20 +210,28 @@ static void spc5_icu_channel_disable(ICUDriver *icup, uint8_t index) {
  * @param[in] index      ICU channel index

  */

 static void spc5_icu_channel_start(ICUDriver *icup, uint8_t index) {

+

   /* Timer disabled.*/

   icup->etimerp->CHANNEL[index].CTRL.B.CNTMODE = 0b000;

+

   /* Clear pending IRQs (if any).*/

   icup->etimerp->CHANNEL[index].STS.R = 0xFFFF;

+

   /* All IRQs and DMA requests disabled.*/

   icup->etimerp->CHANNEL[index].INTDMA.R = 0x0000;

+

   /* Compare Load 1 disabled.*/

   icup->etimerp->CHANNEL[index].CCCTRL.B.CLC1 = 0b000;

+

   /* Compare Load 2 disabled.*/

   icup->etimerp->CHANNEL[index].CCCTRL.B.CLC2 = 0b000;

+

   /* Capture 1 disabled.*/

   icup->etimerp->CHANNEL[index].CCCTRL.B.CPT1MODE = 0b00;

+

   /* Capture 2 disabled.*/

   icup->etimerp->CHANNEL[index].CCCTRL.B.CPT2MODE = 0b00;

+

   /* Counter reset to zero.*/

   icup->etimerp->CHANNEL[index].CNTR.R = 0x0000;

 }

@@ -225,15 +243,17 @@ static void spc5_icu_channel_start(ICUDriver *icup, uint8_t index) {
  * @param[in] index      ICU channel index

  */

 static void spc5_icu_channel_init(ICUDriver *icup, uint8_t index) {

+

 #if !defined(psc)

   uint32_t psc;

 #endif

   psc = (icup->clock / icup->config->frequency);

-  chDbgAssert(

-      (psc <= 0xFFFF) && (((psc) * icup->config->frequency) == icup->clock) &&

-      ((psc == 1) || (psc == 2) || (psc == 4) || (psc == 8) || (psc == 16) ||

-          (psc == 32) || (psc == 64) || (psc == 128)),

-      "icu_lld_start(), #1", "invalid frequency");

+  chDbgAssert((psc <= 0xFFFF) &&

+              (((psc) * icup->config->frequency) == icup->clock) &&

+              ((psc == 1) || (psc == 2) || (psc == 4) ||

+               (psc == 8) || (psc == 16) || (psc == 32) ||

+               (psc == 64) || (psc == 128)),

+              "icu_lld_start(), #1", "invalid frequency");

 

   /* Set primary source and clock prescaler.*/

   switch (psc) {

@@ -262,6 +282,7 @@ static void spc5_icu_channel_init(ICUDriver *icup, uint8_t index) {
     icup->etimerp->CHANNEL[index].CTRL.B.PRISRC = 0b11111;

     break;

   }

+

   /* Set control registers.*/

   icup->etimerp->CHANNEL[index].CTRL.B.ONCE = 0;

   icup->etimerp->CHANNEL[index].CTRL.B.LENGTH = 0;

@@ -314,6 +335,7 @@ static void spc5_icu_channel_init(ICUDriver *icup, uint8_t index) {
  * @param[in] index      ICU channel index

  */

 static void icu_lld_interrupt_management(ICUDriver *icup, uint8_t index) {

+

 #if !defined(sr)

   uint16_t sr;

 #endif

@@ -345,7 +367,7 @@ static void icu_lld_interrupt_management(ICUDriver *icup, uint8_t index) {
         _icu_isr_invoke_width_cb(icup);

       }

     }

-  } else { /* End ICU_SKIP_FIRST_CAPTURE = TRUE*/

+  } else { /* ICU_SKIP_FIRST_CAPTURE = TRUE*/

     if ((sr & 0x0008) != 0) { /* TOF */

       icup->etimerp->CHANNEL[index].STS.B.TOF = 1U;

       _icu_isr_invoke_overflow_cb(icup);

@@ -359,7 +381,7 @@ static void icu_lld_interrupt_management(ICUDriver *icup, uint8_t index) {
       icup->etimerp->CHANNEL[index].STS.B.ICF2 = 1U;

       _icu_isr_invoke_width_cb(icup);

     }

-  } /* End ICU_SKIP_FIRST_CAPTURE = FALSE*/

+  } /* ICU_SKIP_FIRST_CAPTURE = FALSE */

 }

 

 /**

@@ -927,14 +949,14 @@ void icu_lld_init(void) {
  * @notapi

  */

 void icu_lld_start(ICUDriver *icup) {

-  chDbgAssert(

-      (icup->config->channel == ICU_CHANNEL_1) ||

-      (icup->config->channel == ICU_CHANNEL_2) ||

-      (icup->config->channel == ICU_CHANNEL_3) ||

-      (icup->config->channel == ICU_CHANNEL_4) ||

-      (icup->config->channel == ICU_CHANNEL_5) ||

-      (icup->config->channel == ICU_CHANNEL_6),

-      "icu_lld_start(), #1", "invalid input");

+

+  chDbgAssert((icup->config->channel == ICU_CHANNEL_1) ||

+              (icup->config->channel == ICU_CHANNEL_2) ||

+              (icup->config->channel == ICU_CHANNEL_3) ||

+              (icup->config->channel == ICU_CHANNEL_4) ||

+              (icup->config->channel == ICU_CHANNEL_5) ||

+              (icup->config->channel == ICU_CHANNEL_6),

+             "icu_lld_start(), #1", "invalid input");

 

 #if SPC5_ICU_USE_SMOD0 || SPC5_ICU_USE_SMOD1 || SPC5_ICU_USE_SMOD2 ||        \

     SPC5_ICU_USE_SMOD3 || SPC5_ICU_USE_SMOD4 || SPC5_ICU_USE_SMOD5

@@ -1005,7 +1027,7 @@ void icu_lld_start(ICUDriver *icup) {
   SMOD11 = 1U;

 #endif

 

-#if SPC5_ICU_USE_SMOD0 || SPC5_ICU_USE_SMOD1 || SPC5_ICU_USE_SMOD2 ||        \

+#if SPC5_ICU_USE_SMOD0 || SPC5_ICU_USE_SMOD1 || SPC5_ICU_USE_SMOD2 ||       \

     SPC5_ICU_USE_SMOD3 || SPC5_ICU_USE_SMOD4 || SPC5_ICU_USE_SMOD5

   /* Set Peripheral Clock.*/

   if (!(SMOD0 || SMOD1 || SMOD2 || SMOD3 || SMOD4 || SMOD5)) {

@@ -1013,7 +1035,7 @@ void icu_lld_start(ICUDriver *icup) {
                                  SPC5_ICU_ETIMER0_START_PCTL);

   }

 #endif

-#if SPC5_ICU_USE_SMOD6 || SPC5_ICU_USE_SMOD7 || SPC5_ICU_USE_SMOD8 ||        \

+#if SPC5_ICU_USE_SMOD6 || SPC5_ICU_USE_SMOD7 || SPC5_ICU_USE_SMOD8 ||       \

     SPC5_ICU_USE_SMOD9 || SPC5_ICU_USE_SMOD10 || SPC5_ICU_USE_SMOD11

   /* Set Peripheral Clock.*/

   if (!(SMOD6 || SMOD7 || SMOD8 || SMOD9 || SMOD10 || SMOD11)) {

@@ -1239,6 +1261,7 @@ void icu_lld_stop(ICUDriver *icup) {
  * @notapi

  */

 void icu_lld_enable(ICUDriver *icup) {

+

 #if SPC5_ICU_USE_SMOD0

   if (&ICUD1 == icup) {

     spc5_icu_channel_enable(icup, 0);

@@ -1320,6 +1343,7 @@ void icu_lld_enable(ICUDriver *icup) {
  * @notapi

  */

 void icu_lld_disable(ICUDriver *icup) {

+

 #if SPC5_ICU_USE_SMOD0

   if (&ICUD1 == icup) {

     spc5_icu_channel_disable(icup, 0);

@@ -1404,6 +1428,7 @@ void icu_lld_disable(ICUDriver *icup) {
  * @notapi

  */

 icucnt_t icu_lld_get_width(ICUDriver *icup) {

+

   return (icucnt_t)*icup->wccrp + 1;

 }

 

@@ -1418,6 +1443,7 @@ icucnt_t icu_lld_get_width(ICUDriver *icup) {
  * @notapi

  */

 icucnt_t icu_lld_get_period(ICUDriver *icup) {

+

   return (icucnt_t)*icup->pccrp + 1;

 }

 

diff --git a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h b/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h
index bd7ebe5da..4090648e8 100644
--- a/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h
+++ b/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h
@@ -13,8 +13,8 @@
  */

 

 /**

- * @file

- * @brief   SPC5xx low level icu driver header.

+ * @file    eTimer_v1/icu_lld.c

+ * @brief   SPC5xx low level ICU driver header.

  *

  * @addtogroup ICU

  * @{

@@ -56,7 +56,7 @@
  * @note    The default is @p TRUE.

  */

 #if !defined(SPC5_ICU_USE_SMOD0) || defined(__DOXYGEN__)

-#define SPC5_ICU_USE_SMOD0	                 TRUE

+#define SPC5_ICU_USE_SMOD0	                TRUE

 #endif

 

 /**

@@ -65,7 +65,7 @@
  * @note    The default is @p TRUE.

  */

 #if !defined(SPC5_ICU_USE_SMOD1) || defined(__DOXYGEN__)

-#define SPC5_ICU_USE_SMOD1	                 TRUE

+#define SPC5_ICU_USE_SMOD1	                TRUE

 #endif

 

 /**

@@ -74,7 +74,7 @@
  * @note    The default is @p TRUE.

  */

 #if !defined(SPC5_ICU_USE_SMOD2) || defined(__DOXYGEN__)

-#define SPC5_ICU_USE_SMOD2 	                 TRUE

+#define SPC5_ICU_USE_SMOD2 	                TRUE

 #endif

 

 /**

@@ -83,7 +83,7 @@
  * @note    The default is @p TRUE.

  */

 #if !defined(SPC5_ICU_USE_SMOD3) || defined(__DOXYGEN__)

-#define SPC5_ICU_USE_SMOD3 	                 TRUE

+#define SPC5_ICU_USE_SMOD3 	                TRUE

 #endif

 

 /**

@@ -92,7 +92,7 @@
  * @note    The default is @p TRUE.

  */

 #if !defined(SPC5_ICU_USE_SMOD4) || defined(__DOXYGEN__)

-#define SPC5_ICU_USE_SMOD4                   TRUE

+#define SPC5_ICU_USE_SMOD4                  TRUE

 #endif

 

 /**

@@ -101,7 +101,7 @@
  * @note    The default is @p TRUE.

  */

 #if !defined(SPC5_ICU_USE_SMOD5) || defined(__DOXYGEN__)

-#define SPC5_ICU_USE_SMOD5	                 TRUE

+#define SPC5_ICU_USE_SMOD5	                TRUE

 #endif

 

 /**

@@ -110,7 +110,7 @@
  * @note    The default is @p TRUE.

  */

 #if !defined(SPC5_ICU_USE_SMOD6) || defined(__DOXYGEN__)

-#define SPC5_ICU_USE_SMOD6                   TRUE

+#define SPC5_ICU_USE_SMOD6                  TRUE

 #endif

 

 /**

@@ -119,7 +119,7 @@
  * @note    The default is @p TRUE.

  */

 #if !defined(SPC5_ICU_USE_SMOD7) || defined(__DOXYGEN__)

-#define SPC5_ICU_USE_SMOD7                   TRUE

+#define SPC5_ICU_USE_SMOD7                  TRUE

 #endif

 

 /**

@@ -128,7 +128,7 @@
  * @note    The default is @p TRUE.

  */

 #if !defined(SPC5_ICU_USE_SMOD8) || defined(__DOXYGEN__)

-#define SPC5_ICU_USE_SMOD8                   TRUE

+#define SPC5_ICU_USE_SMOD8                  TRUE

 #endif

 

 /**

@@ -137,7 +137,7 @@
  * @note    The default is @p TRUE.

  */

 #if !defined(SPC5_ICU_USE_SMOD9) || defined(__DOXYGEN__)

-#define SPC5_ICU_USE_SMOD9                   TRUE

+#define SPC5_ICU_USE_SMOD9                  TRUE

 #endif

 

 /**

@@ -146,7 +146,7 @@
  * @note    The default is @p TRUE.

  */

 #if !defined(SPC5_ICU_USE_SMOD10) || defined(__DOXYGEN__)

-#define SPC5_ICU_USE_SMOD10                   TRUE

+#define SPC5_ICU_USE_SMOD10                 TRUE

 #endif

 

 /**

@@ -155,21 +155,21 @@
  * @note    The default is @p TRUE.

  */

 #if !defined(SPC5_ICU_USE_SMOD11) || defined(__DOXYGEN__)

-#define SPC5_ICU_USE_SMOD11                   TRUE

+#define SPC5_ICU_USE_SMOD11                 TRUE

 #endif

 

 /**

  * @brief   eTimer0 interrupt priority level setting.

  */

 #if !defined(SPC5_ICU_ETIMER0_PRIORITY) || defined(__DOXYGEN__)

-#define SPC5_ICU_ETIMER0_PRIORITY         7

+#define SPC5_ICU_ETIMER0_PRIORITY           7

 #endif

 

 /**

  * @brief   eTimer1 interrupt priority level setting.

  */

 #if !defined(SPC5_ICU_ETIMER1_PRIORITY) || defined(__DOXYGEN__)

-#define SPC5_ICU_ETIMER1_PRIORITY         7

+#define SPC5_ICU_ETIMER1_PRIORITY           7

 #endif

 

 /**

@@ -263,7 +263,7 @@
  *          are defined in @p hal_lld.h.

  */

 #if !defined(SPC5_ICU_ETIMER0_START_PCTL) || defined(__DOXYGEN__)

-#define SPC5_ICU_ETIMER0_START_PCTL     (SPC5_ME_PCTL_RUN(1) |          \

+#define SPC5_ICU_ETIMER0_START_PCTL         (SPC5_ME_PCTL_RUN(1) |          \

                                              SPC5_ME_PCTL_LP(2))

 #endif

 

@@ -274,7 +274,7 @@
  *          are defined in @p hal_lld.h.

  */

 #if !defined(SPC5_ICU_ETIMER0_STOP_PCTL) || defined(__DOXYGEN__)

-#define SPC5_ICU_ETIMER0_STOP_PCTL      (SPC5_ME_PCTL_RUN(0) |          \

+#define SPC5_ICU_ETIMER0_STOP_PCTL          (SPC5_ME_PCTL_RUN(0) |          \

                                              SPC5_ME_PCTL_LP(0))

 #endif

 

@@ -285,7 +285,7 @@
  *          are defined in @p hal_lld.h.

  */

 #if !defined(SPC5_ICU_ETIMER1_START_PCTL) || defined(__DOXYGEN__)

-#define SPC5_ICU_ETIMER1_START_PCTL     (SPC5_ME_PCTL_RUN(1) |          \

+#define SPC5_ICU_ETIMER1_START_PCTL         (SPC5_ME_PCTL_RUN(1) |          \

                                              SPC5_ME_PCTL_LP(2))

 #endif

 

@@ -296,7 +296,7 @@
  *          are defined in @p hal_lld.h.

  */

 #if !defined(SPC5_ICU_ETIMER1_STOP_PCTL) || defined(__DOXYGEN__)

-#define SPC5_ICU_ETIMER1_STOP_PCTL      (SPC5_ME_PCTL_RUN(0) |          \

+#define SPC5_ICU_ETIMER1_STOP_PCTL          (SPC5_ME_PCTL_RUN(0) |          \

                                              SPC5_ME_PCTL_LP(0))

 #endif

 /** @} */